Senior DV Engineer - Verification Lead for ASIC/FPGA

SBT; San Francisco (CA); On-site; USD 180,000 - 240,000; Full time

Job summary

SBT in San Francisco is seeking a hands-on DV lead to collaborate with systems HW engineers and SW architects in developing cutting-edge computing systems. You will influence the full lifecycle of complex chip development, solving hard verification challenges for tier-one customers.

Responsibilities include verification planning, building test benches and test cases, and creating DV infrastructure for ASIC and FPGA platforms, ensuring alignment with design requirements and enabling robust

Qualifications

• Technical degree in a related engineering field.
• 5–10+ years of relevant industry experience.
• Proficiency in SystemVerilog and UVM.
• Expertise in network switching data path-related technology.

Responsibilities

• Develop verification plans and strategies based on design specifications and requirements.
• Create verification methodologies, test benches, and test cases for RTL designs.
• Define and develop verification infrastructure and tests for ASIC and FPGA platforms.

Skills

SystemVerilog

UVM

Verification methodologies

RTL verification

Education

Electrical engineering degree

Tools

SystemVerilog

UVM

Job description

SBT in San Francisco is seeking a hands-on DV lead to collaborate with systems HW engineers and SW architects in developing cutting-edge computing systems. You will influence the full lifecycle of complex chip development, solving hard verification challenges for tier-one customers.

Responsibilities include verification planning, building test benches and test cases, and creating DV infrastructure for ASIC and FPGA platforms, ensuring alignment with design requirements and enabling robust