Senior DV Engineer - AI-Driven ASIC Verification

Normal Computing; New York, Mountain View (NY, CA); On-site; USD 130,000 - 190,000; Full time

Job summary

Normal Computing is seeking a Design Verification Engineer to verify our physics-inspired ASICs and contribute to AI-assisted verification flows as we approach tapeout.

You will own thermodynamic ASIC verification, review AI-generated collateral, and set up EDA tooling across shared compute resources, collaborating with a team across New York, Silicon Valley, London, and beyond.

This role rewards deep DV craft and clear communication in a fast-moving, collaborative environment.

Qualifications

• 5+ years of experience in digital verification at a major semiconductor or EDA tool company.
• Advanced proficiency in SystemVerilog, UVM methodology, and EDA verification tools (vManager, Xcelium, Jasper), with strong Python or Perl scripting.
• Proven expertise in end-to-end design verification, including test plan creation, stimulus generation, and feature extraction.
• Excellent written and spoken communication skills: you can hold the room in a design review as credibly as you hold a debug session.

Responsibilities

• Thermodynamic ASIC Verification: Own design verification for Normal's internal silicon: testbench environments, assertions, and coverage from design documents through functional coverage and closure, supporting the program to tapeout.
• AI-Assisted Verification: Review AI-generated verification collateral and help define what good looks like, so the tools the team builds raise the bar rather than lower it.
• Tooling: Set up and evaluate EDA tools, ensuring usability and effective deployment on shared computing resources internally.

Skills

Digital verification

SystemVerilog

UVM

Python or Perl scripting

Test planning

Communication skills

Tools

vManager

Xcelium

Jasper

Job description

Normal Computing is seeking a Design Verification Engineer to verify our physics-inspired ASICs and contribute to AI-assisted verification flows as we approach tapeout.

You will own thermodynamic ASIC verification, review AI-generated collateral, and set up EDA tooling across shared compute resources, collaborating with a team across New York, Silicon Valley, London, and beyond.

This role rewards deep DV craft and clear communication in a fast-moving, collaborative environment.