Director, ASIC DV Architecture & Tape-Out

SambaNova; San Jose (CA); On-site; USD 270,000 - 340,000; Full time

Benefits offered by this job

Equity

Health insurance

Well-being benefits

Job summary

SambaNova Systems is seeking a Director of ASIC Design Verification to own end-to-end verification for next-gen RDU chips. Lead a team of 8–10 engineers, set verification architecture, and drive pre-silicon quality through tape-out.

You'll guide methodology, test benches, and coverage strategies, while collaborating with architecture, design, and software teams to validate ML applications on silicon. Strong hands-on DV and leadership are essential.

Qualifications

• BS in EE, CS, or CE with 12+ years in ASIC design verification.
• 5+ years managing design verification engineers, including hiring and performance management.
• Track record of inheriting an established verification environment and evolving it with the team.
• Deep hands-on verification expertise; own methodology, testbench architecture, and sign-off criteria.
• Full-cycle DV from planning through tape-out into production silicon.
• Deep knowledge of SystemVerilog, SVA, Python; familiarity with UVM/OVM/VMM.
• Experience through silicon bring-up and lab validation.
• Knowledge of ML SoCs or CPUs/GPUs and modern architecture.
• Excellent communication and stakeholder alignment.

Responsibilities

• Own verification through tape-out: pre-silicon functional and performance verification — quality, coverage, on-time tape-out.
• Define verification architecture, strategy, schedules, and DV environments for complex ML ASICs.
• Serve as technical authority on verification: arbitrate testbench architecture, set coverage and sign-off criteria, lead debug on hardest failures.
• Set and defend the DV schedule and tape-out readiness sign-off; report risk and readiness to executives with clear POV.
• Carry ownership into first silicon; support lab validation and bring-up debug, feeding findings back to pre-silicon env.

Skills

ASIC DV

Team management

SystemVerilog

SVA

Python

Pre-silicon verification

ML SoCs knowledge

Communication

Education

BS in EE/CS/CE

MS/PhD in EECS

Tools

UVM/OVM/VMM

Emulation

FPGA prototyping

Job description

SambaNova Systems is seeking a Director of ASIC Design Verification to own end-to-end verification for next-gen RDU chips. Lead a team of 8–10 engineers, set verification architecture, and drive pre-silicon quality through tape-out.

You'll guide methodology, test benches, and coverage strategies, while collaborating with architecture, design, and software teams to validate ML applications on silicon. Strong hands-on DV and leadership are essential.