Senior DRAM Design Engineer – Onsite in Boise

Micron Technology Inc; Boise (ID); On-site; USD 140,000 - 210,000; Full time

Benefits offered by this job

Relocation assistance

Job summary

Micron Technology Inc. is seeking a Semiconductor Design Engineer (Principal/Senior Staff) to design and optimize next-generation DRAM products. You will work with global teams to deliver high-performance memory solutions while mentoring engineers and shaping technical direction.

This role is based in Boise, ID, on-site five days a week. Qualifications include a PhD or MS with extensive CMOS design experience, expertise in Verilog, PDN analysis, and scripting with Python/Tcl/Perl.

Qualifications

• Bachelor's degree in Electrical Engineering or related field; MS/PhD preferred for senior tracks
• 10+ years semiconductor design experience for engineer roles; SMTS candidates typically 15+ years with leadership

Responsibilities

• Design and optimize digital and analog circuits for next-generation DRAM products, including memory arrays and I/O circuitry
• Lead circuit development, verification, and silicon validation to meet performance, power, area, and quality targets
• Drive floor-planning, layout optimization, and tape-out activities
• Advance AI-assisted design flows and collaborate with internal/external partners
• Provide technical leadership and mentor other engineers

Skills

CMOS circuit design

Verilog modeling

Python scripting

Tcl scripting

Perl scripting

Analytical thinking

Communication

Multi-functional collaboration

Mentoring engineers

Problem solving

Education

Bachelor's degree in Electrical Engineering

MS in Electrical Engineering

Tools

FINESIM

HSPICE

Job description

Micron Technology Inc. is seeking a Semiconductor Design Engineer (Principal/Senior Staff) to design and optimize next-generation DRAM products. You will work with global teams to deliver high-performance memory solutions while mentoring engineers and shaping technical direction.

This role is based in Boise, ID, on-site five days a week. Qualifications include a PhD or MS with extensive CMOS design experience, expertise in Verilog, PDN analysis, and scripting with Python/Tcl/Perl.