Senior DRAM Design Engineer: Next-Gen Memory Innovator

Micron Technology, Inc; Boise (ID); On-site; USD 140,000 - 200,000; Full time

Job summary

Micron Technology, Inc. in Boise, Idaho invites a Senior DRAM Design Engineer to drive digital and analog memory circuit development.

You will design, analyze, and optimize memory and logic circuits, collaborate with cross-functional teams, and contribute to parasitic modeling and tape-out readiness. The role requires strong Verilog/SPICE experience, familiarity with Synopsys and Cadence tools, and a track record in mixed-signal design for memory technologies.

Qualifications

• Bachelor’s or Master’s degree in Electrical Engineering.
• Minimum 4 years of semiconductor design and development experience.
• Experience with IC modeling and simulation using SPICE and Verilog.
• Working knowledge of Synopsys design tools and Cadence Virtuoso.
• Strong understanding of digital and analog circuit design methodologies.

Responsibilities

• Contribute to the design, layout, verification, and optimization of memory, logic, and analog circuits for new product development.
• Perform parasitic modeling and support design validation, reticle experiments, and tape-out revisions.
• Lead layout activities including floor planning, placement, and routing.
• Partner with Product Engineering, Test, Probe, Assembly, Process Integration, and Marketing teams to ensure manufacturable product designs.
• Collaborate with CAD, modeling, standards, and verification teams to improve design quality and execution.

Skills

Verilog

SPICE

Digital/Analog design

Parasitic modeling

Memory design

Mixed-signal design

Education

Bachelor’s or Master’s degree in Electrical Engineering

Tools

Synopsys tools

Cadence Virtuoso

Job description

Micron Technology, Inc. in Boise, Idaho invites a Senior DRAM Design Engineer to drive digital and analog memory circuit development.

You will design, analyze, and optimize memory and logic circuits, collaborate with cross-functional teams, and contribute to parasitic modeling and tape-out readiness. The role requires strong Verilog/SPICE experience, familiarity with Synopsys and Cadence tools, and a track record in mixed-signal design for memory technologies.