Senior DRAM Design Engineer – Next-Gen HBM for AI

Micron; Richardson (TX); On-site; USD 140,000 - 190,000; Full time

Benefits offered by this job

Medical, dental and vision plans

Paid time-off and holidays

Paid family leave

Job summary

Micron Technology is seeking a Senior Member of Technical Staff / Member of Technical Staff, DRAM Design Engineer in our HBM Architecture team in Richardson, TX. You will drive architecture and optimization of 3D-stacked, high-performance memories for AI workloads.

Responsibilities include identifying novel DRAM architectures, validating hypotheses through schematic design and SPICE simulations, and collaborating with layout and test teams to optimize PPA and yield.

Qualifications

• Strong mixed signal design experience with analog and synthesis flows.
• DRAM circuit design in cell arrays, sense amplifiers, decoders, periphery, IO.
• Experience with SPICE-based tools (FineSim, HSPICE).
• Excellent communication and data-driven analysis skills.

Responsibilities

• Identify and develop novel DRAM circuit architectures for AI workloads and bandwidth/energy efficiency.
• Collaborate to identify bottlenecks and define architectural hypotheses.
• Validate hypotheses via schematic design, SPICE simulation, and tradeoff analysis.
• Partner with layout designers to conduct floorplanning studies.
• Define and optimize design-for-test and design-for-yield implementation.
• Compose and maintain clear architecture specifications and documentation.

Skills

DRAM design

SPICE tools

Sense amplifiers

Row/Column decoders

Verilog

Python

Strong communication

Education

Masters or PhD in EE/CS

Tools

FineSim

HSPICE

Verilog

Python

Perl

Job description

Micron Technology is seeking a Senior Member of Technical Staff / Member of Technical Staff, DRAM Design Engineer in our HBM Architecture team in Richardson, TX. You will drive architecture and optimization of 3D-stacked, high-performance memories for AI workloads.

Responsibilities include identifying novel DRAM architectures, validating hypotheses through schematic design and SPICE simulations, and collaborating with layout and test teams to optimize PPA and yield.