Senior HBM Design Engineer: 3D-Stacked Memory & HPC

Micron Technology; Richardson (TX); On-site; USD 140,000 - 170,000; Full time

Benefits offered by this job

Medical/Dental/Vision

Paid time off

Paid holidays

401(k) plan

Job summary

Micron Technology in Richardson, TX is seeking a Sr Design Engineer to design, simulate, and validate next‑generation High‑Bandwidth Memory (HBM) architectures and DRAM blocks. You will collaborate with global design teams to optimize timing, power, and reliability for AI/ML, HPC, and graphics applications.

You will participate in tape‑out activities, ECOs, and verification using industry tools, ensuring manufacturability and quality across complex 3D-stacked memory systems.

Qualifications

• MS in Computer Engineering or related field.
• 3 years DRAM Design or Verification experience.
• Prior experience in HBM, DRAM, high-speed I/O, or memory-related designs.
• Familiar with device reliability and verification flows.
• Experience in function verification and timing analysis with mixed signal design.

Responsibilities

• Design, optimize, and validate memory blocks and post-silicon bring-up.
• Collaborate with layout engineers on floorplanning, placement, routing, and constraints.
• Review parasitics, EM/IR, and reliability results; drive fixes as needed.
• Ensure designs are manufacturable and meet foundry and packaging requirements.
• Support tape-out activities, ECOs, and reticle experiments as required.
• Participate in functional, timing, and power verification using standard simulation tools.

Skills

HBM design

DRAM design

High-speed I/O

PHY timing

Power integrity

3D stacked architectures

TSV signaling

Education

MS in Computer Engineering

Tools

HSPICE

VerilogHDL

Primesim

Job description

Micron Technology in Richardson, TX is seeking a Sr Design Engineer to design, simulate, and validate next‑generation High‑Bandwidth Memory (HBM) architectures and DRAM blocks. You will collaborate with global design teams to optimize timing, power, and reliability for AI/ML, HPC, and graphics applications.

You will participate in tape‑out activities, ECOs, and verification using industry tools, ensuring manufacturability and quality across complex 3D-stacked memory systems.