Senior DRAM Design Engineer for HBM & AI Workloads

Micron Technology, Inc; Richardson (TX); On-site; USD 140,000 - 200,000; Full time

Job summary

Micron Technology, Inc in the United States is seeking a senior DRAM circuit design engineer to identify and develop novel memory architectures, validate them with SPICE simulations, and collaborate with layout teams on floorplanning and test strategies.

Ideal candidates have 8+ years in DRAM design, experience with HBM or stacked memories, and proficiency in Verilog and Python; a Master's or PhD in EE/CS is preferred. This role offers impactful work on AI memory systems.

Qualifications

• Strong mixed-signal design experience, including analog and synthesis flows.
• DRAM circuit design experience in cell arrays, sense amps, decoders, IO, or power distribution.
• Proficient with SPICE-based tools (e.g., FineSim, HSPICE) and data-driven analysis.
• Excellent communication to influence peers.

Responsibilities

• Identify and develop novel DRAM circuit architectures to improve bandwidth and energy efficiency.
• Collaborate to identify bottlenecks and define architectural hypotheses.
• Validate hypotheses via schematic-level design, SPICE, and trade-off analysis.
• Partner with layout designers to conduct floorplanning studies.
• Define and optimize design-for-test and design-for-yield implementations.
• Compose and maintain clear specifications and architecture documentation.

Skills

Mixed-signal design

DRAM circuit design

Cell arrays

Sense amplifiers

Row/Column decoders

Periphery

IO

Power distribution

Communication skills

Education

Master's degree in Electrical Engineering

PhD in Electrical Engineering or related field

Tools

SPICE (FineSim, HSPICE)

Verilog

Python

Perl

Job description

Micron Technology, Inc in the United States is seeking a senior DRAM circuit design engineer to identify and develop novel memory architectures, validate them with SPICE simulations, and collaborate with layout teams on floorplanning and test strategies.

Ideal candidates have 8+ years in DRAM design, experience with HBM or stacked memories, and proficiency in Verilog and Python; a Master's or PhD in EE/CS is preferred. This role offers impactful work on AI memory systems.