Senior IC Verification Engineer | PCIe, UVM & Coverage

Broadcom; San Jose (CA); On-site; USD 122,000 - 195,000; Full time

Benefits offered by this job

Medical/Dental/Vision insurance

401(k) with company match

ESPP – Employee Stock Purchase Program

Paid holidays, sick leave and vacation

Job summary

Broadcom in San Jose, CA seeks an experienced verification engineer to develop test plans for Block/Core/SOC features and to build scalable, reusable test benches within a rigorous verification framework. The role requires crafting pseudo-random tests to maximize coverage and debugging regression failures while closing coverage gaps.

The candidate must have deep verification knowledge, including test plans, verification environments, and experience with SystemVerilog and verification

Qualifications

• Bachelor's degree in Electrical Engineering or related field required.
• 6+ years of experience in writing and debugging complex test benches.
• Deep understanding of Verification from building testbenches to functional coverage.
• Proficiency in SystemVerilog and verification methodologies like UVM/VMM/OVM.
• Strong object-oriented programming skills.
• Knowledge of PCI Express protocol is desirable.

Responsibilities

• Develop test plans for all features for Block/Core/SOC and write functional coverage.
• Architect and develop scalable and reusable test benches using verification methodology frameworks.
• Build pseudo-random tests to verify and achieve full functional coverage.
• Debug regression failures, analyze coverage gaps and improve tests.
• Lead documentation of verification strategy including test plans and verification environment.
• Drive improvements in verification quality and efficiency.

Skills

Object-Oriented Programming

Independent work

Problem solving

Education

Bachelor's degree in Electrical Engineering or related field

Master's degree in Electrical Engineering or related field

Tools

SystemVerilog

UVM

VMM

OVM

PCIe

Job description

Broadcom in San Jose, CA seeks an experienced verification engineer to develop test plans for Block/Core/SOC features and to build scalable, reusable test benches within a rigorous verification framework. The role requires crafting pseudo-random tests to maximize coverage and debugging regression failures while closing coverage gaps.

The candidate must have deep verification knowledge, including test plans, verification environments, and experience with SystemVerilog and verification