SoC Design Verification Engineer — UVM & RTL Expert

L&T Technology Services; San Jose (CA); On-site; USD 140,000 - 200,000; Full time

Benefits offered by this job

Paid Leave

Health Insurance

Group life Insurance

Disability

401(K)

Job summary

L&T Technology Services in San Jose seeks DV verification engineers to verify complex internal IP blocks within SoC environments, focusing on compute engines, accelerators, and custom logic. You will develop UVM-based verification environments, create test plans and coverage models, verify RTL designs, debug testbenches, and drive coverage closure across functional and code domains.

Strong hands-on with SystemVerilog and UVM, plus experience in block-level verification and debugging tools, are

Qualifications

• Strong hands-on with SystemVerilog and UVM.
• Experience in block-level verification.
• Good understanding of digital design fundamentals.
• Experience with debug tools (Verdi, DVE, etc.)

Responsibilities

• Develop and maintain UVM-based verification environments
• Create test plans, testcases, and coverage models
• Perform functional verification of RTL designs
• Debug RTL and testbench issues
• Drive coverage closure (functional + code)

Skills

SystemVerilog

UVM

Block-level verification

Digital design fundamentals

Debug tools

Tools

Verdi

DVE

Job description

L&T Technology Services in San Jose seeks DV verification engineers to verify complex internal IP blocks within SoC environments, focusing on compute engines, accelerators, and custom logic. You will develop UVM-based verification environments, create test plans and coverage models, verify RTL designs, debug testbenches, and drive coverage closure across functional and code domains.

Strong hands-on with SystemVerilog and UVM, plus experience in block-level verification and debugging tools, are