Lead Design Verification Engineer: SystemVerilog/UVM & DDR6

Renesas; Plano (TX); On-site; USD 140,000 - 210,000; Full time

Job summary

Renesas Plano is seeking a Principal Design Verification Engineer to provide technical leadership for verification of next‑generation memory interface products, including data buffer silicon. You will drive verification strategy and execution for complex digital designs, collaborating with design teams to ensure functionality and performance meet requirements.

The ideal candidate has deep semiconductor verification expertise with SystemVerilog and UVM, and experience guiding verification plans

Qualifications

• Bachelor's or Master's degree in Electrical/Computer Engineering, Computer Engineering, Computer Science, or a related technical field.
• Extensive semiconductor design verification experience with ownership of complex verification efforts.
• Expert-level proficiency with SystemVerilog.
• Significant hands-on experience with UVM and verification environments.
• Experience defining verification strategies and developing verification plans.

Responsibilities

• Lead verification strategy and execution for complex semiconductor designs at the block and system level.
• Define verification methodologies, test plans, coverage strategies, and verification environments.
• Architect and maintain SystemVerilog/UVM testbenches and verification environments.
• Drive test development, functional coverage, checkers, constrained-random verification, and coverage closure.
• Own verification for assigned blocks from planning through signoff.
• Collaborate with RTL/design engineers to meet functional and performance requirements.
• Analyze specifications and verification results to identify issues and gaps.
• Lead debugging of complex verification failures.
• Develop reusable verification components and best practices.
• Identify and drive improvements in verification efficiency and quality.

Skills

Technical leadership

Mentoring

Communication

Problem solving

Education

Bachelor's or Master's in Electrical/Computer Engineering or related

Tools

SystemVerilog

UVM

Job description

Renesas Plano is seeking a Principal Design Verification Engineer to provide technical leadership for verification of next‑generation memory interface products, including data buffer silicon. You will drive verification strategy and execution for complex digital designs, collaborating with design teams to ensure functionality and performance meet requirements.

The ideal candidate has deep semiconductor verification expertise with SystemVerilog and UVM, and experience guiding verification plans