Lead SystemVerilog/UVM Verification Architect – DDR6

Renesas Electronics Corp.; Plano (TX); On-site; USD 140,000 - 190,000; Full time

Job summary

Renesas Electronics Corp. in Plano, TX is seeking a Principal Design Verification Engineer to lead verification strategy and execution for next‑generation memory interface products, including data buffers and DDR IP.

You will own verification of complex digital designs at the block and system levels, collaborating with RTL/design engineers to ensure quality and sign‑off. The ideal candidate has deep SystemVerilog and UVM experience, strong technical leadership, and a track record of driving

Qualifications

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field.
• Extensive experience in semiconductor design verification with ownership of complex verification efforts.
• Expert-level proficiency with SystemVerilog.

Responsibilities

• Lead verification strategy and execution for complex semiconductor designs at the block and system level.
• Define verification methodologies, test plans, coverage strategies, and verification environments.
• Architect, develop and optimize SystemVerilog/UVM testbenches and verification environments.
• Drive test development, functional coverage, checkers, constrained-random verification, and coverage closure.
• Take technical ownership of verification for assigned blocks, features, and environments from planning through signoff.
• Work with RTL/design engineers to ensure designs meet functional and performance requirements and are verifiable.
• Communicate verification progress, risks, and readiness to leadership and stakeholders.

Skills

SystemVerilog

UVM

Verification strategy

Mentoring

Education

Electrical/Computer Engineering

Job description

Renesas Electronics Corp. in Plano, TX is seeking a Principal Design Verification Engineer to lead verification strategy and execution for next‑generation memory interface products, including data buffers and DDR IP.

You will own verification of complex digital designs at the block and system levels, collaborating with RTL/design engineers to ensure quality and sign‑off. The ideal candidate has deep SystemVerilog and UVM experience, strong technical leadership, and a track record of driving