Senior Digital ASIC Engineer — High-Performance, Low-Power

Inuplands; Cambridge (MA); On-site; USD 82,300 - 220,000; Full time

Job summary

Draper Laboratory seeks a Senior Digital ASIC Designer to deliver high-performance digital ASICs in advanced technologies. You will implement designs from RTL through synthesis, work with multi-disciplinary teams, and contribute to multiple projects across applications.

The role requires strong front-end digital design skills, experience with Cadence or Synopsys, and the ability to lead teams. An active US secret clearance is required for onsite work in Cambridge, MA.

Qualifications

• Proficiency in digital IC design and RTL-to-silicon flow.
• Experience with advanced CMOS nodes; knowledge of layout considerations.
• Front-end digital systems design with Cadence or Synopsys workflows.

Responsibilities

• Design and simulate circuits at transistor level to meet specs.
• Contribute to system-level design and architectural reviews.
• Optimize designs for performance, power, and cost.
• Lead multi-disciplinary teams and drive complex IC projects.
• Prepare design documentation and mentor junior engineers.

Skills

Integrated circuit design

SystemVerilog/Verilog/VHDL

Front-end digital design

Cadence or Synopsys design flows

Technical leadership

Communication skills

Time management

Education

Bachelor's degree in Engineering

Master's degree preferred

Tools

Cadence

Synopsys

Job description

Draper Laboratory seeks a Senior Digital ASIC Designer to deliver high-performance digital ASICs in advanced technologies. You will implement designs from RTL through synthesis, work with multi-disciplinary teams, and contribute to multiple projects across applications.

The role requires strong front-end digital design skills, experience with Cadence or Synopsys, and the ability to lead teams. An active US secret clearance is required for onsite work in Cambridge, MA.