Senior Digital Design Engineer - Memory RTL & PPA

Micron Technology, Inc; Boise (ID); On-site; USD 120,000 - 180,000; Full time

Benefits offered by this job

Medical plan

Dental plan

Vision plan

Paid time off

Paid holidays

Retirement benefits

Job summary

Micron Technology, Inc. is a leading memory solutions company seeking a Senior Digital Design Engineer to advance DRAM digital and mixed-signal blocks. You will handle RTL design, synthesis, timing analysis, and power optimization across the RTL-to-GDS flow.

You will collaborate with architecture, verification, and physical design teams to deliver high-performance, power-efficient designs that meet product specifications and PPA objectives for next‑generation memory products.

Qualifications

• Master’s degree in Electrical Engineering (or equivalent) with 4+ years of experience, or Bachelor’s degree with 5+ years of experience in digital ASIC/RTL design.
• Proven experience developing RTL for complex digital designs from specification through implementation handoff.
• Strong knowledge of ASIC front-end design flows including RTL design, functional verification, logic synthesis, CDC/RDC analysis, and static timing analysis (STA).
• Experience developing and maintaining design constraints (SDC), including clocks, timing exceptions, I/O constraints, and multi-mode multi-corner timing scenarios.
• Proficiency with Verilog/SystemVerilog and industry-standard simulation tools.
• Experience with low-power design methodologies, UPF-based power intent, timing constraints, and PPA optimization.

Responsibilities

• Design, develop, and deliver RTL for complex DRAM digital and mixed-signal blocks.
• Perform front-end design quality checks including linting, CDC/RDC analysis, logic synthesis, timing constraint development, and timing closure activities.
• Collaborate with architecture, verification, and physical design teams to optimize power, performance, area (PPA), and overall design quality.
• Develop and maintain synthesis and timing constraints (SDC), analyze timing reports, and drive timing closure across multiple operating scenarios.
• Improve design methodologies, automation, and RTL-to-GDS flows to enhance development efficiency, design quality, and time-to-market.

Skills

Verilog/SystemVerilog

RTL design

Synthesis

Timing analysis

Power optimization

Education

Master's degree in Electrical Engineering

Bachelor's degree in Electrical Engineering

Tools

Verilog tools

Job description

Micron Technology, Inc. is a leading memory solutions company seeking a Senior Digital Design Engineer to advance DRAM digital and mixed-signal blocks. You will handle RTL design, synthesis, timing analysis, and power optimization across the RTL-to-GDS flow.

You will collaborate with architecture, verification, and physical design teams to deliver high-performance, power-efficient designs that meet product specifications and PPA objectives for next‑generation memory products.