Sr Digital Design Engineer

Micron Technology

Boise (ID)

On-site

USD 120,000 - 160,000

Full time

45 hours ago
Be an early applicant

Get more replies from employers

Send a job-specific resume in minutes.

Job summary

Micron Technology in Boise, Idaho seeks a Senior Digital Design Engineer to contribute to the RTL-to-GDS flow for next‑gen DRAM digital and mixed-signal blocks. You will design RTL, perform synthesis, timing analysis, and power optimization to meet product specifications and PPA targets.

The role collaborates with architecture, verification and physical design teams to deliver high-performance, power-efficient designs and drive time-to-market.

Qualifications

  • Master’s degree with 4+ years of experience or Bachelor’s with 5+ years in digital ASIC/RTL design.
  • Proven RTL development experience from specification through implementation handoff.
  • Strong knowledge of front-end ASIC design flows: RTL, verification, synthesis, STA.
  • Experience creating and maintaining design constraints (SDC) with clocks and multi‑mode timing.
  • Proficiency with Verilog/SystemVerilog and industry-standard simulation tools.
  • Experience with UPF-based power intent and PPA optimization.

Responsibilities

  • Design, develop, and deliver RTL for complex DRAM digital/mixed-signal blocks.
  • Perform linting, CDC/RDC analysis, synthesis, timing constraints, and timing closure.
  • Collaborate with architecture, verification, and physical design teams to optimize PPA.
  • Maintain synthesis and timing constraints (SDC) and drive timing closure across scenarios.
  • Improve RTL methodologies, automation, and RTL-to-GDS flow for efficiency.

Skills

RTL design
Verilog/SystemVerilog
STA
CDC/RDC analysis
Synthesis
PPA optimization

Education

Master’s degree in Electrical Engineering
Bachelor’s degree in Electrical Engineering

Tools

Simulation tools

Job description

Our vision is to transform how the world uses information to enrich life for all.

Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.

Job Summary

Micron is seeking a Senior Digital Design Engineer to contribute to the development of advanced DRAM digital and mixed-signal blocks. This role is responsible for RTL design, implementation, synthesis, timing analysis, power optimization, and design quality throughout the RTL-to-GDS flow. The engineer will collaborate with architecture, verification, and physical design teams to deliver high-performance, power-efficient designs that meet product specifications and PPA (Power, Performance, Area) objectives for next-generation memory products.

Responsibilities
  • Design, develop, and deliver RTL for complex DRAM digital and mixed-signal blocks, ensuring alignment with product specifications and performance targets.
  • Perform front-end design quality checks including linting, CDC/RDC analysis, logic synthesis, timing constraint development, and timing closure activities.
  • Collaborate with architecture, verification, and physical design teams to optimize power, performance, area (PPA), and overall design quality.
  • Develop and maintain synthesis and timing constraints (SDC), analyze timing reports, and drive timing closure across multiple operating scenarios.
  • Improve design methodologies, automation, and RTL-to-GDS flows to enhance development efficiency, design quality, and time-to-market.
Minimum Qualifications
  • Master’s degree in Electrical Engineering (or equivalent) with 4+ years of experience, or Bachelor’s degree with 5+ years of experience in digital ASIC/RTL design.
  • Proven experience developing RTL for complex digital designs from specification through implementation handoff.
  • Strong knowledge of ASIC front-end design flows including RTL design, functional verification, logic synthesis, CDC/RDC analysis, and static timing analysis (STA).
  • Experience developing and maintaining design constraints (SDC), including clocks, timing exceptions, I/O constraints, and multi-mode multi-corner timing scenarios
  • Proficiency with Verilog/SystemVerilog and industry-standard simulation tools.
  • Experience with low-power design methodologies, UPF-based power intent, timing constraints, and PPA optimization.
Preferred Qualifications
  • Experience developing RTL for memory products or other high-performance digital designs.
  • Familiarity with CMOS digital and mixed‑signal circuit concepts.
  • Experience collaborating across architecture, verification, and physical implementation teams to resolve integration and design challenges.
  • Demonstrated ability to improve engineering productivity through process improvements, automation, and enhanced design methodologies.
  • Strong communication, problem-solving, and teamwork skills, with the ability to demonstrate AI-assisted technologies and generative AI tools to improve engineering efficiency and collaboration.

As a world leader in the semiconductor industry, Micron is dedicated to your personal wellbeing and professional growth. Micron benefits are designed to help you stay well, provide peace of mind and help you prepare for the future. We offer a choice of medical, dental and vision plans in all locations enabling team members to select the plans that best meet their family healthcare needs and budget. Micron also provides benefit programs that help protect your income if you are unable to work due to illness or injury, and paid family leave. Additionally, Micron benefits include a robust paid time-off program and paid holidays. For additional information regarding the Benefit programs available, please see the Benefits Guide posted on micron.com/careers/benefits.

Micron is proud to be an equal opportunity workplace and is an affirmative action employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, age, national origin, citizenship status, disability, protected veteran status, gender identity or any other factor protected by applicable federal, state, or local laws.

Micron Prohibits the use of child labor and complies with all applicable laws, rules, regulations, and other international and industry labor standards.

Micron does not charge candidates any recruitment fees or unlawfully collect any other payment from candidates as consideration for their employment with Micron.

AI alert: Candidates are encouraged to use AI tools to enhance their resume and/or application materials. However, all information provided must be accurate and reflect the candidate's true skills and experiences. Misuse of AI to fabricate or misrepresent qualifications will result in immediate disqualification.

Fraud alert: Micron advises job seekers to be cautious of unsolicited job offers and to verify the authenticity of any communication claiming to be from Micron by checking the official Micron careers website in the About Micron Technology, Inc.

Get your free, confidential resume review.
or drag and drop your file here.
Similar jobs

Similar jobs worth comparing

Sr Digital Design Engineer
Sr Digital Design Engineer

1000 Micron Technology, Inc. • Boise (ID)

On-site
USD 120,000 - 180,000
Medical, dental, and vision plans
Paid time off & holidays
Benefits Guide
Sr Digital Design Engineer
Sr Digital Design Engineer

Micron Technology, Inc • Boise (ID)

On-site
USD 110,000 - 170,000
Medical, dental and vision plans
Paid time-off
Paid holidays
SrvDigital Design Engineer
SrvDigital Design Engineer

Micron Technology, Inc • Boise (ID)

On-site
USD 120,000 - 180,000
Medical plan
Dental plan
Vision plan
+3
Senior Circuit Design Engineer, DRAM
Senior Circuit Design Engineer, DRAM

Micron Technology • Boise (ID)

On-site
USD 120,000 - 180,000
Medical, dental and vision plans
Paid time off
Paid holidays
Principal RTL Design
Principal RTL Design

Micron Technology • Boise (ID)

On-site
USD 120,000 - 160,000
Medical, dental, and vision plans
Paid family leave
Robust paid time-off program
+1
Staff Digital Design Engineer, HBM
Staff Digital Design Engineer, HBM

Micron Technology • Richardson (TX)

On-site
USD 110,000 - 160,000
Sr Design Engineer, DEG Design Method
Sr Design Engineer, DEG Design Method

Micron Technology • Boise (ID)

On-site
USD 110,000 - 150,000
Medical, dental and vision plans
Paid time off
Paid holidays
PRINCIPAL RTL DESIGN
PRINCIPAL RTL DESIGN

Micron Technology • Boise (ID)

On-site
USD 140,000 - 190,000
Medical plans
Dental plans
Vision plans
+2
Design Engineer - DRAM Technology and Products
Design Engineer - DRAM Technology and Products

Micron Technology, Inc. • Boise (ID)

On-site
USD 110,000 - 150,000
Staff Design Engineer, DRAM
Staff Design Engineer, DRAM

Micron Technology • Boise (ID)

On-site
USD 120,000 - 180,000