Digital Design Engineer (Tech Lead)

Astera Labs; San Jose (CA); On-site; USD 140,000 - 190,000; Full time

Benefits offered by this job

Flexible time off in the US

Parental leave

401K

Retirement and pension plans

Competitive medical, dental and vision

Job summary

Astera Labs seeks a Senior Digital Design Engineer in the United States to develop micro-architecture and front-end circuit design, including RTL, synthesis, and IP integration for high-performance network controllers.

The role requires strong knowledge of PCI-Express, Ethernet, and related protocols, with hands-on experience in verification, bring-up, and debug across complex SoC blocks.

Qualifications

• Bachelor’s degree in EE required; Master’s preferred.
• Strong background in electrical engineering and front-end SoC design.
• Experience with PCIe, Uplink, Esun, Ethernet protocols.

Responsibilities

• Develop micro-architecture and front-end circuit design (RTL, synthesis, timing).
• Lead block-level verification from architecture to GDS.
• Support or develop complex SoC/silicon products for networking/server applications.

Skills

RTL design

Synthesis

IP integration

Front-end verification

High-speed protocols

Python scripting

Education

Bachelor's in EE

Master's degree preferred

Tools

Synopsys tools

Cadence tools

Verilog/VHDL

Job description

• We are looking for Senior Digital Design Engineers with experience developing micro-architecture and implementation of the front-end circuit design, including RTL, synthesis, IP integration, and block-level verification for high performance network controllers

Benefits

• Flexible time off in the US
• Parental leave
• 401K
• Retirement and pension plans
• Competitive medical, dental and vision plans

The candidate must have good knowledge of communication/interface protocols such as PCI-Express (Gen-3 and above), Ualink, Esun, Ethernet etc+3 years’ experience supporting or developing complex SoC/silicon products for Switch ASIC, Networking applications and/or Server, StorageProfessional attitude with the ability to prioritize a dynamic list of multiple tasks, plan and prepare for customer meetings in advance, and work with minimal guidance and supervisionEntrepreneurial, open-mind behavior and can-do attitude. Think and act fast with the customer in mind!Strong academic and technical background in electrical engineering. A Bachelor’s degree in EE is required, and a Master’s degree is preferredAuthorized to work in the US and start immediatelyKnowledge of design for test (DFT)Proven front end design skill – architecture, RTL, simulations, synthesis, timing closure, GLS, DFT etcSilicon bring-up and debug experienceFamiliarity with UVM based design verificationBlock level ownership from architecture to GDSExperience with Synopsys and/or Cadence digital design tools/flowsSmall-geometry CMOS (≤28nm) designHands-on, thorough knowledge of high-speed protocols like PCIe, Ualink, Esun, Ethernet, etcScripting with Python or other equivalent programming languagesDevelopment/support for PCIe or Ethernet Switch products