Senior Manager, Front‑End Digital IC Design—PCIe/CXL

Asteralabs; San Jose (CA); On-site; USD 216,000 - 240,000; Full time

Job summary

Astera Labs is seeking a Senior Manager/Manager, Digital Design to lead front-end digital design for PCIe, CXL, UAL and Ethernet devices powering rack-scale AI infrastructure. You will drive RTL development, verification, timing, and tape-out from requirements to production.

You will manage a team of 6–8 engineers, partner with architecture and systems teams, ensure quality and on-time delivery, and influence cross-functional decisions while delivering high-performance, power-efficient silicon.

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, or related field.
• 3–5 years of engineering management or technical leadership in digital IC/ASIC design.
• Experience leading front-end RTL development and tape-out readiness.
• Proven ownership of chip design from requirements through production.

Responsibilities

• Lead end-to-end chip development from requirements through tape-out and shipment.
• Ensure RTL quality, timing closure, and smooth tape-out readiness.
• Mentor a 6–8 person digital design team and drive cross-functional collaboration.

Skills

PCIe & CXL experience

RTL design leadership

Front-end RTL development

Engineering leadership

Education

Bachelor's degree in Electrical Engineering, Computer Engineering, or related field

Master's or PhD in Electrical/Computer Engineering or related field

Job description

Astera Labs is seeking a Senior Manager/Manager, Digital Design to lead front-end digital design for PCIe, CXL, UAL and Ethernet devices powering rack-scale AI infrastructure. You will drive RTL development, verification, timing, and tape-out from requirements to production.

You will manage a team of 6–8 engineers, partner with architecture and systems teams, ensure quality and on-time delivery, and influence cross-functional decisions while delivering high-performance, power-efficient silicon.