Lead Design Verification Engineer - SerDes/PHY IP

Astera Labs; San Jose (CA); Hybrid; USD 160,000 - 200,000; Full time

Job summary

Astera Labs in San Jose seeks a Principal Design Verification Engineer to own functional verification of high-speed SerDes/PHY IP powering rack-scale AI infra. You will architect verification environments, drive coverage closure, and ensure first-pass silicon success on the analog/digital boundary.

You will partner with PHY analog/mixed-signal designers, digital architects, and SoC teams to verify multi-Gbps SerDes blocks targeting PCIe Gen6/Gen7, UALink, UCIe, and Ethernet.

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, or related field.
• 5+ years of design verification experience on high-speed SerDes, PHY, or mixed-signal IP.
• Expert-level proficiency in SystemVerilog and UVM.

Responsibilities

• Architect UVM-based verification environments for SerDes/PHY IP, including PMA, PCS, and PHY-MAC interface layers.
• Define verification plans, coverage models, and sign-off criteria for high-speed serial link blocks.
• Drive methodology decisions across analog/mixed-signal co-simulation, gate-level simulation, and emulation flows.
• Develop SystemVerilog/UVM testbenches, sequences, scoreboards, and reference models for multi-Gbps SerDes lanes.
• Execute functional, performance, and corner-case verification across equalization, CDR, training, and link bring-up scenarios.
• Lead coverage analysis and closure, debug failures with designers, and drive regressions to clean tape-out.
• Verify PHY behavior against PCIe Gen 6/Gen 7, UALink, UCIe, and Ethernet PHY standards.
• Model and validate channel behavior, link training state machines, and analog handoff scenarios.
• Partner with analog/AMS designers on RNM and behavioral models for SerDes blocks.

Skills

SystemVerilog

UVM

Co-simulation

RNM

High-speed protocols

Education

Bachelor's degree in Electrical/Computer Engineering

MS or PhD in Electrical/Computer Engineering

Job description

Astera Labs in San Jose seeks a Principal Design Verification Engineer to own functional verification of high-speed SerDes/PHY IP powering rack-scale AI infra. You will architect verification environments, drive coverage closure, and ensure first-pass silicon success on the analog/digital boundary.

You will partner with PHY analog/mixed-signal designers, digital architects, and SoC teams to verify multi-Gbps SerDes blocks targeting PCIe Gen6/Gen7, UALink, UCIe, and Ethernet.