Principal Digital Design Engineer — AI Connectivity Architect

Astera Labs; San Jose (CA); Hybrid; USD 185,000 - 230,000; Full time

Job summary

Astera Labs in San Jose, CA, is hiring a Principal/ Sr.Principal Digital Design Engineer to architect and implement next-generation digital designs for high-performance AI connectivity solutions.

You will own complex blocks from micro-architecture through silicon bring-up, drive RTL implementation, and collaborate with verification, physical design, and DFT teams to deliver production-quality silicon supporting PCIe Gen6/Gen7, CXL, UALink, UCI, Ethernet, and DDR4/DDR5.

Qualifications

• Bachelor's degree in Electrical Engineering or equivalent.
• 10+ years of hands-on experience developing complex SoC/silicon products in Server, Storage, and/or Networking markets.
• Expertise in architecture definition, micro-architecture development, RTL coding, functional simulation, and synthesis.
• Strong understanding of timing closure, gate-level simulation (GLS), and DFT implementation.
• Deep expertise in at least one high-speed protocol: PCIe, CXL, Ethernet, DDR, or similar.
• Production experience with advanced CMOS nodes (≤7nm).
• Proficiency with Cadence and/or Synopsys digital design flows

Responsibilities

• Design Ownership & Execution
• Develop and implement complex digital blocks and subsystems by defining micro-architecture and driving RTL implementation with an exceptional power, performance and area trade-off using silicon technologies better than 7nm.
• Lead efforts to achieve timing closure and implement Design-for-Test (DFT) features for optimal design performance
• Drive designs to production, ensuring accountability for quality, schedule, and overall design success
• Verification & Integration
• Collaborate with verification teams to develop test plans, achieve coverage closure, and debug complex issues
• Own third-party IP integration and block-level verification through sign-off
• Work closely with post-silicon teams to facilitate silicon bring-up and debug
• Technical Leadership
• Mentor junior engineers to develop their technical skills and expertise
• Actively contribute to the development and improvement of silicon development processes
• Drive design methodology improvements and CAD automation initiatives

Skills

RTL coding

Timing closure

DFT

High-speed protocols

Architecture definition

Synthesis

Verification planning

Education

Bachelor's degree in electrical engineering

Master's degree in Electrical Engineering

Tools

Cadence

Synopsys

Job description

Astera Labs in San Jose, CA, is hiring a Principal/ Sr.Principal Digital Design Engineer to architect and implement next-generation digital designs for high-performance AI connectivity solutions.

You will own complex blocks from micro-architecture through silicon bring-up, drive RTL implementation, and collaborate with verification, physical design, and DFT teams to deliver production-quality silicon supporting PCIe Gen6/Gen7, CXL, UALink, UCI, Ethernet, and DDR4/DDR5.