Senior DFT & Test Lead: Design-for-Test Architect

Celestica; Richardson (TX); On-site; USD 120,000 - 160,000; Full time

Job summary

Celestica is seeking a Sr. Lead, DFT and Test Engineer to ensure testability and maximum test coverage are embedded into hardware design long before layout freeze.

In this role within our DFx Center of Excellence, you will perform in-design testability reviews, audit test point access and boundary scan chains, and model functional coverage against manufacturing targets to drive high-yield, debug-ready releases.

Qualifications

• Bachelor degree or equivalent combination of education and experience.
• 4 to 6 years in a similar role or industry.
• In-design testability reviews and audit test point access.

Responsibilities

• Pre-Freeze Audits: review schematics and PCBs against DFT rules and document findings.
• Coverage Modeling: model structural/functional coverage vs. MTRS and quantify gaps.
• Finding Disposition: work with hardware and software teams to resolve issues via design changes.
• Validation & Verification: confirm coverage on the first fixture and document discrepancies.
• Site Support: assist with functional test definitions and early build debug.
• Rule Evolution: propose DFT rule updates from test escapes.

Skills

DFT

Testability

Boundary Scan

MTRS Coverage Modeling

Test Point Accessibility

Hardware Bring-Up

DFx Center of Excellence

Design for Testability (DFT)

Education

Bachelor degree

Tools

Boundary Scan Tools

Test Equipment

Job description

Celestica is seeking a Sr. Lead, DFT and Test Engineer to ensure testability and maximum test coverage are embedded into hardware design long before layout freeze.

In this role within our DFx Center of Excellence, you will perform in-design testability reviews, audit test point access and boundary scan chains, and model functional coverage against manufacturing targets to drive high-yield, debug-ready releases.