Senior Test Engineering Lead: DFT & Boundary Scan

Celestica; Richardson (TX); On-site; USD 180,000 - 240,000; Full time

Job summary

Celestica is seeking a Senior Manager of HPS Test Engineering in Richardson, TX to own end-to-end testing architecture, strategy, and execution for next‑generation products and infrastructure. This role bridges silicone design, hardware/software teams, and volume manufacturing.

You will lead a high‑performing team of test hardware and software engineers, drive DFT/DFx reviews early in design, collaborate with silicon partners, and optimize test coverage, yield, and throughput across ICT, FCT,

Qualifications

• 8+ years of dedicated engineering experience in test development, functional testing architecture, ATE hardware, or NPI test leadership.
• Experience deploying complex test vectors for high‑speed digital systems, enterprise servers, or hyperscaler infrastructure.
• Strong knowledge of DFT methodologies, IEEE 1149.x Boundary Scan (JTAG), PCIe Gen5/6, SerDes, instrumentation automation, and data mining for SPC.

Responsibilities

• Lead and mentor a multi-disciplinary team of test hardware and software engineers.
• Define and drive end-to-end test strategy, architecture, and KPIs.
• Engage with silicon partners to embed BIST, high‑speed boundary scan, and diagnostic hooks.
• Oversee test plan architecture, coverage matrices, and test point allocations.
• Drive yield optimization through data analytics and fixture design improvements.

Skills

People leadership

Test architecture

DFT/Boundary Scan

Program management

Python/C/C++

JTAG/PCIe SerDes

Data analytics

Education

Bachelor’s or Master’s in Electrical Engineering

Tools

LabVIEW

Python

Job description

Celestica is seeking a Senior Manager of HPS Test Engineering in Richardson, TX to own end-to-end testing architecture, strategy, and execution for next‑generation products and infrastructure. This role bridges silicone design, hardware/software teams, and volume manufacturing.

You will lead a high‑performing team of test hardware and software engineers, drive DFT/DFx reviews early in design, collaborate with silicon partners, and optimize test coverage, yield, and throughput across ICT, FCT,