Lead ASIC DFT Architect & Debug Engineer

Socket.dev; United States; Remote; USD 180,000 - 240,000; Full time

Job summary

Socket.dev seeks a highly experienced Lead ASIC DFT Engineer to architect, implement, verify, and debug advanced DFT solutions for complex ASIC and SoC designs. This role requires technical ownership across DFT architecture, scan insertion, ATPG, and post-silicon validation.

The ideal candidate will lead cross-functional teams, drive testability, and improve robustness, quality, and yield with emerging DFT methodologies.

Qualifications

• Strong hands-on experience in ASIC DFT with end-to-end ownership.
• Deep understanding of DFT fundamentals and fault models.
• Experience with scan architecture, ATPG, MBIST/LBIST, and silicon debug.
• Familiarity with RTL, synthesis, and physical design impacts on DFT.

Responsibilities

• Lead DFT architecture, implementation, verification, and sign-off for ASIC/SoC designs.
• Drive scan architecture, scan insertion, scan chain stitching, and compression workflows.
• Own MBIST/LBIST integration, verification, and debug across bring-up phases.
• Perform DFT debug, fault analysis, root-cause investigation, and coverage closure.
• Develop and validate DFT constraints, including DFT SDC and timing checks.
• Collaborate with RTL, verification, physical design, and silicon validation teams.
• Support ATPG pattern generation, simulations, DRC analysis, and test coverage.
• Work on JTAG, boundary scan, iJTAG, SSN, and IP-level DFT integration.
• Review RTL/synthesis/LEC/physical design impacts on DFT and test quality.
• Mentor junior/mid-level engineers and promote DFT automation.
• Develop TCL/PERL/Python scripts to improve flow efficiency and debugging productivity.

Skills

DFT fundamentals

ATPG

MBIST

LBIST

JTAG

Boundary scan

Silicon debug

Scan insertion

Dysdiagnosis

Tools

Synopsys tools

Cadence tools

Siemens/Mentor EDA

Job description

Socket.dev seeks a highly experienced Lead ASIC DFT Engineer to architect, implement, verify, and debug advanced DFT solutions for complex ASIC and SoC designs. This role requires technical ownership across DFT architecture, scan insertion, ATPG, and post-silicon validation.

The ideal candidate will lead cross-functional teams, drive testability, and improve robustness, quality, and yield with emerging DFT methodologies.