Senior ASIC DFT Lead - Test & Post-Silicon Debug

Links Technology Solutions, Inc.; Carlsbad (CA); Hybrid; USD 110,000 - 124,000; Full time

Benefits offered by this job

Health insurance

Life insurance

Vision insurance

Dental insurance

401K Matching

Job summary

Links Technology Solutions, Inc. in Carlsbad, CA, is seeking an ASIC Design for Test Lead (DFT) to drive design-for-test features and debug. The role focuses on ATPG, scan, BIST, and boundary scan, ensuring high quality, manufacturable silicon while supporting post-silicon qualification.

As a DFT Lead, you will collaborate across teams, guide DFT methodology, and lead root cause analysis of silicon failures to improve yield and reliability throughout the product life cycle.

Qualifications

• Bachelor's or Master's in Electrical or Computer Engineering.
• Experience with JTAG, Scan and BIST architectures including memory BIST and boundary scan.
• Experience with ATPG and EDA tools Tessent, Xcelium, Genus, Tempus/Primetime.
• Hands-on post-silicon debug of DFT patterns - scan, mbist, boundary scan and release to production.
• Ability to train teams on DFT methodologies from design phase to high volume production.

Responsibilities

• Implement DFT features: scan, mbist, BISR, boundary scan, and DFT simulations debugging.
• Develop innovative DFT IP and integrate with RTL for testability.
• Collaborate across multi-functional teams on new silicon device models and reusable test/debug strategies.
• Lead debugging and root cause analysis of silicon failures to improve yield and reliability.

Skills

JTAG protocols

Scan architectures

Memory BIST

Boundary scan

ATPG

Post-silicon debug

EDA tools

Tessent

Xcelium

Genus

Education

Bachelor's or Master's in Electrical or Computer Engineering

Tools

Tessent tool sets

Xcelium

Genus

Tempus/Primetime

Job description

Links Technology Solutions, Inc. in Carlsbad, CA, is seeking an ASIC Design for Test Lead (DFT) to drive design-for-test features and debug. The role focuses on ATPG, scan, BIST, and boundary scan, ensuring high quality, manufacturable silicon while supporting post-silicon qualification.

As a DFT Lead, you will collaborate across teams, guide DFT methodology, and lead root cause analysis of silicon failures to improve yield and reliability throughout the product life cycle.