Lead DFT Architect for Next-Gen ASICs

Normal Computing Corporation; Palo Alto (CA); Presencial; USD 180 000 - 240 000; Tempo integral

Vantagens oferecidas por esta oferta de emprego

DFT architecture startup (bonus)

IEEE 1687 familiarity (IJTAG)

Memory redundancy / BISR knowledge

External DFT partner management

AI-assisted design tools

Exposure to AI accelerators

Resumo da oferta

Normal Computing is hiring a Design-for-Test (DFT) Engineer to own the DFT architecture and implementation for next‑gen, physics‑inspired ASICs. You will guide scan/ATPG, MBIST, and boundary‑scan strategies and work with RTL, verification, physical design, and silicon product engineering teams.

You will establish DFT methodologies, lead external partners, and ensure designs are ready for manufacturing test, shaping DFT infrastructure for a new silicon class while driving scalable flows and

Qualificações

• 7+ years of experience in DFT implementation for complex ASICs or SoCs, including successful tapeouts.
• Strong hands‑on expertise in scan insertion, ATPG, scan compression, fault coverage analysis, and test pattern generation.
• Proven experience with MBIST, boundary scan/JTAG, and DFT integration across RTL and gate‑level designs.
• Proficiency with industry‑standard DFT tools such as Siemens Tessent, Synopsys TestMAX, or Cadence Modus.
• Solid understanding of RTL design, synthesis, static timing analysis, and physical design considerations.
• Experience delivering manufacturing test patterns and collaborating with silicon product engineering or ATE teams.
• Strong scripting skills in Python, Tcl, or similar languages.
• Ability to independently own DFT architecture, drive cross‑functional technical decisions, and communicate effectively across design, verification, and product engineering teams.

Responsabilidades

• Own DFT architecture, define chip‑level DFT architecture including scan insertion, ATPG, scan compression, MBIST, boundary scan/JTAG, and test access infrastructure.
• Drive DFT insertion and integration across RTL, synthesis, and physical design, ensuring testability requirements are met without compromising power, performance, or area.
• Own DFT verification, ATPG pattern generation, fault coverage analysis, test‑mode validation, and DFT signoff through tapeout.
• Partner with Head of Silicon Product Engineering to deliver production‑ready test patterns and test collateral to manufacturing partners, and documentation for ATE integration, silicon bring‑up, and diagnosis.
• Establish scalable DFT flows, automation, and best practices using industry‑standard EDA tools.
• Define technical requirements, oversee contracted DFT work, and review deliverables to ensure quality and integration with Normal’s silicon development process.

Conhecimentos

DFT implementation

Scan insertion

ATPG

MBIST

Boundary scan/JTAG

Test pattern generation

RTL design/synthesis

Scripting: Python Tcl

Cross-functional collaboration

Communication across teams

Ferramentas

Siemens Tessent

Synopsys TestMAX

Cadence Modus

Descrição da oferta de emprego

Normal Computing is hiring a Design-for-Test (DFT) Engineer to own the DFT architecture and implementation for next‑gen, physics‑inspired ASICs. You will guide scan/ATPG, MBIST, and boundary‑scan strategies and work with RTL, verification, physical design, and silicon product engineering teams.

You will establish DFT methodologies, lead external partners, and ensure designs are ready for manufacturing test, shaping DFT infrastructure for a new silicon class while driving scalable flows and