Remote DFT Design Lead for ASICs

itD Tech; Arizona; Hybrid; USD 150,000 - 230,000; Full time

Benefits offered by this job

Medical benefits

401K + matching

Paid holidays

Career learning & development

Job summary

itD Tech is seeking a Design-for-Test (DFT) Lead to drive advanced DFT solutions across the silicon development lifecycle, ensuring testable, manufacturable ASIC designs. The role requires deep DFT expertise, post-silicon validation, and leadership to resolve complex challenges.

The position offers hybrid work options in Carlsbad, CA or Allentown, PA or US remote, with Pacific Time hours. A 14-month duration and comprehensive benefits are included; sponsorship is not available.

Qualifications

• Bachelor's or Master's degree in Electrical or Computer Engineering or a related field.
• 8–10+ years of ASIC DFT engineering experience.
• Hands-on experience with JTAG, scan architectures, MBIST, BISR, boundary scan and IP integration.
• Experience with ATPG methodologies and EDA tools (Tessent, Xcelium, Genus, Tempus/PrimeTime).
• Experience with post-silicon debug of DFT patterns and production release.

Responsibilities

• Lead hardware DFT feature implementation (scan, MBIST, BISR, boundary scan, DFT sim setup).
• Develop DFT IP with cross-functional teams and integrate into full-chip RTL designs.
• Perform post-silicon debug, root-cause analysis and production qualification to improve yield and manufacturability.
• Collaborate with physical design, validation, and hardware teams throughout the silicon lifecycle.
• Design, validate and release ATPG patterns for manufacturing test readiness and ramp.

Skills

DFT engineering

JTAG/scan architectures

MBIST/BISR

ATPG methodologies

post-silicon debugging

ASIC design & test

strong problem-solving

Education

Bachelor's or Master's in EE/CE

Tools

Tessent

Xcelium

Genus

Tempus

PrimeTime

Job description

itD Tech is seeking a Design-for-Test (DFT) Lead to drive advanced DFT solutions across the silicon development lifecycle, ensuring testable, manufacturable ASIC designs. The role requires deep DFT expertise, post-silicon validation, and leadership to resolve complex challenges.

The position offers hybrid work options in Carlsbad, CA or Allentown, PA or US remote, with Pacific Time hours. A 14-month duration and comprehensive benefits are included; sponsorship is not available.