Senior DFT & ATPG Engineer for SoC/ASIC

AllianceIT Inc; Santa Clara (CA); On-site; USD 120,000 - 160,000; Full time

Job summary

AllianceIT Inc is seeking a seasoned DFT/ATPG engineer to drive testability for complex SoC/ASIC designs in a fast-paced environment. You will apply ATPG pattern generation, analysis, and debug to ensure robust fault coverage.

The role requires strong RTL fundamentals, clock DFT knowledge, MBIST experience, and proficiency with industry-standard DFT/ATPG EDA tools, plus effective communication in high-performance programs.

Qualifications

• 5+ years of hands-on experience in DFT and ATPG for SoC or ASIC designs.
• Strong understanding of DFT fundamentals including controllability, observability, and scan-based testing.
• Proven expertise in ATPG pattern generation, analysis, and debug.
• Experience with MBIST, including memory test architectures and diagnostics.
• Knowledge of IO Test methodologies for interface and pin level validation.
• Solid understanding of clock DFT and clock verification concepts.
• Strong grasp of digital design and RTL fundamentals.
• Experience with industry standard DFT/ATPG EDA tools.
• Ability to work effectively in fast paced, high performance semiconductor programs.
• Strong analytical, problem solving, and communication skills.

Skills

DFT/ATPG for SoC/ASIC

DFT fundamentals

ATPG pattern generation

MBIST

IO Test methodologies

Clock DFT

RTL fundamentals

DFT/ATPG EDA tools

Fast-paced programs

Analytical & communication skills

Job description

AllianceIT Inc is seeking a seasoned DFT/ATPG engineer to drive testability for complex SoC/ASIC designs in a fast-paced environment. You will apply ATPG pattern generation, analysis, and debug to ensure robust fault coverage.

The role requires strong RTL fundamentals, clock DFT knowledge, MBIST experience, and proficiency with industry-standard DFT/ATPG EDA tools, plus effective communication in high-performance programs.