Senior DFT Engineer – ASIC ATPG & Scan Optimization

Mirafra Technology; Tempe (AZ); On-site; USD 100,000 - 130,000; Full time

Job summary

A leading software service organization in Tempe, Arizona seeks a qualified individual with extensive experience in design for test (DFT) for ASICs. The ideal candidate will possess at least 10 years of DFT experience for large scale ASICs and knowledge of Mentor Graphics tools. Responsibilities include generating ATPG, analyzing coverage results, and running gate simulations to verify functionality. Competitive compensation and a dynamic work environment are offered.

Qualifications

• 5 years of experience in DFT in ASICs required.
• 10 years of experience in DFT for large scale ASICs preferred.

Responsibilities

• Generate ATPG and analyze coverage results.
• Run gate simulation to verify scan patterns.

Skills

Design for test (DFT) structures knowledge

Gate simulation

ATPG generation and analysis

Tools

Mentor Graphics DFT tools

Job description

A leading software service organization in Tempe, Arizona seeks a qualified individual with extensive experience in design for test (DFT) for ASICs. The ideal candidate will possess at least 10 years of DFT experience for large scale ASICs and knowledge of Mentor Graphics tools. Responsibilities include generating ATPG, analyzing coverage results, and running gate simulations to verify functionality. Competitive compensation and a dynamic work environment are offered.