Senior ASIC DFT Engineer - Lead Debug & Validation (Remote)

Accord Technologies Inc; San Jose (CA); On-site; USD 150,000 - 180,000; Full time

Job summary

Accord Technologies Inc is seeking a Lead ASIC DFT Engineer in San Jose, CA. This position involves architecting and implementing DFT solutions for complex ASIC and SoC designs. With a requirement of over 10 years of experience in DFT, the candidate must be proficient in scan architecture, JTAG, ATPG, and silicon debug. The work setup is remote with monthly in-office meetings. Strong knowledge of Synopsys, Cadence, and other EDA tools is preferred, along with scripting experience in TCL, PERL, or Python.

Qualifications

• 10+ years of hands-on experience in ASIC Design-for-Test (DFT).
• Experience leading cross-functional debug efforts.
• Proven expertise in silicon bring-up.

Responsibilities

• Architect, implement, verify, and debug advanced DFT solutions.
• Lead technical ownership across DFT architecture.
• Drive resolution of critical silicon issues.

Skills

ASIC DFT experience

Scan architecture

ATPG

MBIST

JTAG

Boundary scan

Silicon debug

Python scripting

Tools

Synopsys

Cadence

Siemens/Mentor EDA tools

Job description

Accord Technologies Inc is seeking a Lead ASIC DFT Engineer in San Jose, CA. This position involves architecting and implementing DFT solutions for complex ASIC and SoC designs. With a requirement of over 10 years of experience in DFT, the candidate must be proficient in scan architecture, JTAG, ATPG, and silicon debug. The work setup is remote with monthly in-office meetings. Strong knowledge of Synopsys, Cadence, and other EDA tools is preferred, along with scripting experience in TCL, PERL, or Python.