Senior ASIC DFT Engineer – Test & Silicon Innovation

Jobtailor; California (MO); On-site; USD 130,000 - 190,000; Full time

Job summary

Jobtailor is seeking an experienced Hardware DFT Engineer to lead test-data path development for ASIC devices, collaborating across design, verification, and manufacturing teams to ensure robust in-system test and diagnostics from concept to post‑silicon validation.

You will own DFT IP development, implement features for JTAG, boundary scan and memory BIST, validate with ATPG tools, work with gate-level simulation (VCS) and ATE patterns (P1687), and mentor peers while driving technical

Qualifications

• Bachelor's or Master's degree in Electrical or Computer Engineering.
• At least 5 years of experience in DFT, test and silicon engineering.
• Experience with JTAG protocols, scan and BIST architectures, including memory BIST and boundary scan.
• Experience with ATPG and EDA tools like TestMax, Tetramax, Tessent, PrimeTime.
• Experience with gate level simulation and debugging with VCS and other simulators.
• Post-silicon validation and debug experience.
• Ability to work with ATE patterns, P1687.

Responsibilities

• Implement DFT features to support ATE, in-system test, debug and diagnostics.
• Develop innovative DFT IP with cross-functional teams.
• Enable integration and validation of test logic in all implementation and post-silicon validation phases.
• Contribute to hardware DFT and physical design for new silicon models, bare and stacked dies.
• Craft solutions and debug with minimal mentorship.

Skills

DFT Implementation

Test Logic Integration

Gate Level Simulation

Debugging with VCS

Memory BIST

Boundary Scan

ATE Patterns

P1687

Innovative DFT Development

Silicon Engineering

Education

Bachelor's degree in Electrical Engineering

Master's degree in Computer Engineering

Tools

TestMax

Tetramax

Tessent

PrimeTime

VCS

Job description

Jobtailor is seeking an experienced Hardware DFT Engineer to lead test-data path development for ASIC devices, collaborating across design, verification, and manufacturing teams to ensure robust in-system test and diagnostics from concept to post‑silicon validation.

You will own DFT IP development, implement features for JTAG, boundary scan and memory BIST, validate with ATPG tools, work with gate-level simulation (VCS) and ATE patterns (P1687), and mentor peers while driving technical