Senior DFT Design Engineer for ML Acceleration SoCs

Amazon Web Services (AWS)

Austin (TX)

On-site

USD 159,000 - 215,000

Full time

33 hours ago
Be an early applicant

Get more replies from employers

Send a job-specific resume in minutes.

Job summary

Annapurna Labs (U.S.) Inc. in the United States is seeking a Sr. DFT Design Engineer to design and optimize DFT for advanced ASICs in Cloud-Scale ML acceleration.

You will collaborate with PD, Architecture, and Product Engineering to align schedules and deliver high-quality DFT from RTL to silicon. The role requires 5+ years in ASIC design, strong scripting skills, and in-depth DFT knowledge (ATPG, JTAG, MBIST).

Qualifications

  • Bachelor's degree in computer science, electrical engineering, or related field.
  • 5+ years of practical semiconductor ASIC design work including owning end to end design of major SOC blocks.
  • Knowledge about industry standard DFT, including ATPG, JTAG, MBIST and trade-offs between test quality and test time.
  • Experience with automation script development.

Responsibilities

  • Define and develop state-of-the-art Design for Test (DFT) architectures for advanced technology nodes.
  • Work closely with block designers and physical design (PD) team to implement highly efficient DFT solutions.
  • Act as the primary point of contact for cross-functional stakeholders (PD, Architecture, and Product Engineering) to align schedules and goals.
  • Mentor and develop junior engineers through code reviews, methodology training, and technical guidance.
  • Manage project timelines and deliverables, ensuring high-quality DFT implementation from RTL through Silicon bring-up.

Education

Bachelor's degree in CS/EE or related field
Master's or Ph.D. in EE/CS or related field

Tools

Perl
Python
Tcl

Job description

Annapurna Labs (U.S.) Inc. in the United States is seeking a Sr. DFT Design Engineer to design and optimize DFT for advanced ASICs in Cloud-Scale ML acceleration.

You will collaborate with PD, Architecture, and Product Engineering to align schedules and deliver high-quality DFT from RTL to silicon. The role requires 5+ years in ASIC design, strong scripting skills, and in-depth DFT knowledge (ATPG, JTAG, MBIST).

Get your free, confidential resume review.
or drag and drop your file here.
Similar jobs

Similar jobs worth comparing

DFT Design Engineer I for Cloud ML Acceleration
DFT Design Engineer I for Cloud ML Acceleration

Amazon Web Services (AWS) • Austin (TX)

On-site
USD 104,000 - 185,000
Senior DFT Test Infra Engineer for AI/ML ASICs
Senior DFT Test Infra Engineer for AI/ML ASICs

Google • Sunnyvale (CA)

On-site
USD 156,000 - 229,000
Lead ASIC DFT Engineer
Lead ASIC DFT Engineer

ITMC Systems, Inc • San Jose (CA)

On-site
USD 130,000 - 160,000
Principal DFT Engineer for SoC & HBM
Principal DFT Engineer for SoC & HBM

Jobtailor • California (MO)

On-site
USD 140,000 - 200,000
DFT Design Engineer I, AWS Machine Learning Acceleration
DFT Design Engineer I, AWS Machine Learning Acceleration

Amazon Web Services (AWS) • Austin (TX)

On-site
USD 104,000 - 185,000
Senior DFT Engineer - AI Photonics ASICs
Senior DFT Engineer - AI Photonics ASICs

Lightmatter • Mountain View (CA)

Hybrid
USD 164,000 - 185,000
Health care plan
Retirement Savings Matching Program
Life Insurance
+7
Senior ASIC & SOC Integration Manager
Senior ASIC & SOC Integration Manager

Amazon Web Services (AWS) • Cupertino (CA)

On-site
USD 239,600 - 324,100
Lead ASIC DFT Engineer
Lead ASIC DFT Engineer

Accord Technologies Inc • San Jose (CA)

On-site
USD 130,000 - 170,000
Senior DFT Architect for High-Performance SoCs
Senior DFT Architect for High-Performance SoCs

QFocus Technologies • Sunnyvale (CA)

On-site
USD 140,000 - 190,000
ASIC Design-for-Test (DFT)
ASIC Design-for-Test (DFT)

Accord Technologies Inc • San Jose (CA)

On-site
USD 150,000 - 200,000