Senior DFT Design Engineer for ML Acceleration SoCs

Amazon Web Services (AWS)

Austin (TX)

On-site

USD 159,000 - 215,000

Full time

14 days+
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Job summary

Annapurna Labs (U.S.) Inc. in the United States is seeking a Sr. DFT Design Engineer to design and optimize DFT for advanced ASICs in Cloud-Scale ML acceleration.

You will collaborate with PD, Architecture, and Product Engineering to align schedules and deliver high-quality DFT from RTL to silicon. The role requires 5+ years in ASIC design, strong scripting skills, and in-depth DFT knowledge (ATPG, JTAG, MBIST).

Qualifications

  • Bachelor's degree in computer science, electrical engineering, or related field.
  • 5+ years of practical semiconductor ASIC design work including owning end to end design of major SOC blocks.
  • Knowledge about industry standard DFT, including ATPG, JTAG, MBIST and trade-offs between test quality and test time.
  • Experience with automation script development.

Responsibilities

  • Define and develop state-of-the-art Design for Test (DFT) architectures for advanced technology nodes.
  • Work closely with block designers and physical design (PD) team to implement highly efficient DFT solutions.
  • Act as the primary point of contact for cross-functional stakeholders (PD, Architecture, and Product Engineering) to align schedules and goals.
  • Mentor and develop junior engineers through code reviews, methodology training, and technical guidance.
  • Manage project timelines and deliverables, ensuring high-quality DFT implementation from RTL through Silicon bring-up.

Education

Bachelor's degree in CS/EE or related field
Master's or Ph.D. in EE/CS or related field

Tools

Perl
Python
Tcl

Job description

Annapurna Labs (U.S.) Inc. in the United States is seeking a Sr. DFT Design Engineer to design and optimize DFT for advanced ASICs in Cloud-Scale ML acceleration.

You will collaborate with PD, Architecture, and Product Engineering to align schedules and deliver high-quality DFT from RTL to silicon. The role requires 5+ years in ASIC design, strong scripting skills, and in-depth DFT knowledge (ATPG, JTAG, MBIST).

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