DFT Design Engineer for ML Acceleration ASICs

Amazon Web Services (AWS); Austin (TX); On-site; USD 136,000 - 184,000; Full time

Job summary

Annapurna Labs (U.S.) Inc. in Austin, Texas, is seeking an ASIC DFT Design Engineer to design and optimize DFT architectures for advanced SoCs used in AWS data centers.

You will collaborate with block designers and PD teams, implement RTL in Verilog/SystemVerilog and push high-coverage test patterns for silicon at scale. This role requires a Bachelor's in Electrical/Communications Eng, 5+ years in DFT, experience with ATPG/JTAG/MBIST, and scripting.

Qualifications

• Bachelor's degree in Electrical or Communications Engineering or a related field.
• 5+ years of practical DFT experience with complex SoC designs in advanced technology nodes.
• Experience with ATPG, JTAG, MBIST and trade-offs between test quality and test time.
• Experience with automation script development.

Responsibilities

• Define and develop state-of-the-art Design for Test (DFT) architectures for advanced technology nodes.
• Work closely with block designers and physical design (PD) team to implement highly efficient DFT solutions.
• Perform RTL coding and Verification using Verilog/System Verilog.
• Utilize industry standard DFT tools to create high coverage and cost-effective test patterns to target advanced silicon defects.
• Participate in Silicon debug efforts alongside ATE and System teams.
• Communicate and work with team members across multiple disciplines.

Skills

DFT design

ATPG

JTAG

MBIST

Automation scripting

Education

Bachelor's degree in Electrical or Communications Engineering

Master's degree in Electrical or Communications Engineering

Tools

Verilog

SystemVerilog

Job description

Annapurna Labs (U.S.) Inc. in Austin, Texas, is seeking an ASIC DFT Design Engineer to design and optimize DFT architectures for advanced SoCs used in AWS data centers.

You will collaborate with block designers and PD teams, implement RTL in Verilog/SystemVerilog and push high-coverage test patterns for silicon at scale. This role requires a Bachelor's in Electrical/Communications Eng, 5+ years in DFT, experience with ATPG/JTAG/MBIST, and scripting.