Lead ASIC DFT Engineer

SAPSOL Technologies Inc.; United States; On-site; USD 180,000 - 250,000; Full time

Job summary

SAPSOL Technologies Inc. is seeking a Lead ASIC DFT Engineer to architect, implement, verify, and debug advanced DFT solutions for complex ASIC and SoC designs.

The role demands deep technical ownership across DFT architecture, scan insertion, ATPG, MBIST/LBIST, JTAG, boundary scan, and post-silicon validation. The ideal candidate will have hands-on experience with Synopsys, Cadence, and Siemens/Mentor EDA tools, and a proven ability to lead cross-functional debug efforts to resolve critical

Qualifications

• Strong hands-on experience with ASIC DFT end-to-end ownership.

Responsibilities

• Architect, implement, verify and debug advanced DFT solutions for complex ASIC/SoC designs.
• Lead cross-functional debug efforts and drive resolution of silicon issues.
• Provide deep DFT expertise across architecture, scan insertion, ATPG, MBIST/LBIST, JTAG and boundary scan.

Skills

DFT architecture

ATPG

MBIST/LBIST

JTAG boundary scan

EDA tools

RTL design

Physical design

SoC debug

Issue diagnosis

Communication

Tools

Synopsys

Cadence

Mentor Graphics

Job description

We are seeking a highly experienced Lead ASIC DFT Engineer to architect, implement, verify, and debug advanced DFT solutions for complex ASIC and SoC designs. This role requires deep technical ownership across DFT architecture, scan insertion, ATPG, MBIST/LBIST, JTAG, boundary scan, and post-silicon validation, along with the ability to lead cross-functional debug efforts and drive resolution of critical silicon issues. The ideal candidate will have strong hands-on expertise in DFT fundamentals, fault models, test coverage, diagnosis, and debug, as well as the ability to evaluate and adopt emerging DFT methodologies and architecture schemes to improve robustness, quality, and yield.

Requirements Required Skills & Qualifications

• Strong hands-on experience in ASIC DFT with end-to-end ownership.
• Solid understanding of DFT fundamentals, fault models, test techniques, and test coverage concepts.
• Deep expertise in scan architecture, ATPG, MBIST, LBIST, JTAG, boundary scan, and silicon debug.
• Hands-on experience with Synopsys, Cadence, and Siemens/Mentor EDA tools.
• Proven experience in scan insertion, ATPG setup, simulation, debug, and DRC analysis.
• Experience with MBIST implementation and verification; SMS experience preferred.
• Experience with scan architecture and scan chain stitching; Tessent/SSN experience preferred.
• Strong understanding of PLLs, RTL design, synthesis flows, logical equivalence checking (LEC), and physical design implementation.
• Proven post-silicon debug and silicon bring-up experience.
• Exposure to large SoC designs, hierarchical DFT flows, and multi-domain integration challenges.
• Strong communication skills and the ability to work independently with minimal ramp-up.

Originally posted on Himalayas