DFT Design Engineer, ML Acceleration — RSU Eligible

Amazon Inc.; Austin (TX); Vor Ort; USD 136.000 - 184.000; Vollzeit

Benefits dieser Stelle

Sign-on payments

Restricted Stock Units (RSUs)

Health insurance

401(k) matching

Paid time off

Parental leave

Zusammenfassung

Amazon is seeking an ASIC DFT Design Engineer to design and optimize DFT architectures for advanced technology nodes in AWS ML servers. You will help trailblaze new techniques while ensuring high design quality and efficient trade-offs in test cost.

Collaborate with block designers and PD teams, perform RTL coding in Verilog/SystemVerilog, and use standard DFT tools to achieve high coverage and robust testing for large-scale AI silicon.

Qualifikationen

• Bachelor's degree in Electrical or Communications Engineering or related field.
• 5+ years of practical DFT experience with complex SoC designs in advanced technology nodes.
• Experience with ATPG, JTAG, MBIST and trade-offs between test quality and test time.
• Experience with automation script development.

Aufgaben

• Define and develop state-of-the-art DFT architectures for advanced technology nodes.
• Collaborate with block designers and PD teams to implement DFT solutions.
• Perform RTL coding and verification using Verilog/SystemVerilog.
• Utilize industry standard DFT tools to create high-coverage test patterns for silicon defects.
• Support Silicon debug efforts with ATE and System teams.
• Communicate with team members across disciplines.

Kenntnisse

DFT

ATPG

JTAG

MBIST

Verilog

SystemVerilog

RTL coding

Python

Perl

Tcl

DV flows

gate-level simulation

silicon debug

Ausbildung

Bachelor's degree in Electrical or Communications Engineering

Master's degree in Electrical or Communications Engineering

Tools

Verilog

SystemVerilog

SDF

Jobbeschreibung

Amazon is seeking an ASIC DFT Design Engineer to design and optimize DFT architectures for advanced technology nodes in AWS ML servers. You will help trailblaze new techniques while ensuring high design quality and efficient trade-offs in test cost.

Collaborate with block designers and PD teams, perform RTL coding in Verilog/SystemVerilog, and use standard DFT tools to achieve high coverage and robust testing for large-scale AI silicon.