Senior ASIC Designer — Cloud ML Acceleration

Amazon Web Services (AWS); Austin (TX); On-site; USD 159,000 - 215,000; Full time

Job summary

Annapurna Labs (U.S.) Inc. within AWS seeks an experienced ASIC Design Engineer to advance hardware for cloud-scale ML servers. You will design and optimize RTL-based SystemVerilog blocks, analyze microarchitectures, and ensure timing-clean implementations while collaborating with cross-functional teams.

The role emphasizes high performance, low power, and scalable SoC integration in data-centre environments, with opportunities for mentorship and career growth.

Qualifications

• Bachelor's degree in Electrical Engineering or related field.
• 5+ years in RTL design for SOC.
• 5+ years of VLSI engineering.
• 5+ years with code quality tools (Spyglass, LINT, CDC).
• Experience with SystemVerilog RTL and SDC constraints (preferred).

Responsibilities

• Integrate subsystems into top-level SOC and manage clock/reset/DFT routing.
• Deliver high performance, area- and power-efficient RTL to meet targets.
• Analyze design choices for power, performance, and area trade-offs.
• Develop micro-architecture and implement RTL with timing-accurate synthesis.
• Collaborate with architects, verification, and back-end teams.

Skills

RTL design

VLSI engineering

Code quality tools

SystemVerilog

Clock domain

Debugging RTL

Python scripting

Education

Bachelor's degree in Electrical Engineering

Master's or Ph.D. in Electrical Engineering

Tools

Spyglass

LINT

CDC

Job description

Annapurna Labs (U.S.) Inc. within AWS seeks an experienced ASIC Design Engineer to advance hardware for cloud-scale ML servers. You will design and optimize RTL-based SystemVerilog blocks, analyze microarchitectures, and ensure timing-clean implementations while collaborating with cross-functional teams.

The role emphasizes high performance, low power, and scalable SoC integration in data-centre environments, with opportunities for mentorship and career growth.