Senior DFT Design Engineer, GPU/SoC Validation (Hybrid)

Intel Corporation; Hillsboro (OR); Hybrid; USD 142,000 - 173,000; Full time

Job summary

Intel Corporation in the United States currently seeks a Senior DFT Design Engineer to contribute to graphics IP blocks, RTL/GLS validation, and ATPG content analysis for GPU integration. You will influence architecture, optimize RTL, and support high-quality SoC design for post-silicon debugging and verification.

The role emphasizes Scan/ATPG expertise, DFT feature knowledge, and experience with EDA tools like Tessent and VCS.

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, or related STEM degree and 4+ years of industry experience.
• Scan, ATPG or other DFT features.
• SoC or IP DFT design, integration or verification.
• EDA tools such as Siemens Tessent or other ATPG tools, Synopsis VCS and/or other simulation or debug tools.

Responsibilities

• Design, RTL/GLS validation, automation, and/or timing analysis for Scan/ATPG.
• Contribute to trace/pattern generation and post-silicon enabling, debug support, and ATPG content analysis.
• Develop RTL and RTL coding, and simulation for graphics IPs for GPU IP block integration.
• Define architecture and microarchitecture features of the block being designed.
• Write RTL and optimize logic to meet power, performance, area, and timing goals.

Skills

Scan, ATPG, DFT features

Design automation

Programming or scripting

3D, media & display graphics pipelines

SoC architecture

Education

Bachelor's degree in Electrical/Computer Engineering or related STEM

Master's degree in Electrical/Computer Engineering or related STEM

PhD in Electrical/Computer Engineering or related STEM

Tools

Siemens Tessent

Synopsys VCS

Job description

Intel Corporation in the United States currently seeks a Senior DFT Design Engineer to contribute to graphics IP blocks, RTL/GLS validation, and ATPG content analysis for GPU integration. You will influence architecture, optimize RTL, and support high-quality SoC design for post-silicon debugging and verification.

The role emphasizes Scan/ATPG expertise, DFT feature knowledge, and experience with EDA tools like Tessent and VCS.