Senior DFT Architect for SoC & Chiplet IP

TYLsemi; San Jose (CA); On-site; USD 238,000 - 286,000; Full time

Job summary

TYLsemi, Inc. in the United States seeks an experienced DFT Architect to lead design-for-test strategy across complex ASIC/SOC designs, defining SOC-level DFT architecture and implementing scan, MBIST, compression, and boundary scan.

You will collaborate with RTL, Physical Design, Verification, and Product Engineering to drive DFT planning, signoff, and optimizations, while mentoring junior engineers and advancing automation across projects.

Qualifications

• 10+ years of ASIC/SOC DFT implementation and architecture.
• Strong expertise in scan, ATPG, MBIST, JTAG, compression, and low-power DFT.
• Hands-on experience with Tessent and other DFT tools.
• Good understanding of RTL design, timing, PD constraints, and silicon debug.

Responsibilities

• Define and own SOC-level DFT architecture and test strategy for complex semiconductor designs.
• Lead implementation of scan insertion, ATPG, MBIST, LBIST, boundary scan, and test compression methodologies.
• Drive DFT planning and integration aligned with power, timing, area, and test coverage goals.
• Collaborate with RTL, Physical Design, Verification, and Product Engineering teams for seamless DFT integration and signoff.
• Analyze and resolve DFT-related timing, routing, and testability challenges.
• Support silicon bring-up, debug, diagnosis, yield analysis, and production test optimization.
• Develop and enhance DFT automation flows, methodologies, and reusable infrastructure.
• Mentor junior engineers and provide technical leadership across projects.

Skills

DFT architecture

Leadership

ATPG

MBIST

JTAG

Education

Bachelors/Masters in EE or VLSI

Tools

Siemens Tessent

Synopsys DFT Compiler/TestMAX

Job description

TYLsemi, Inc. in the United States seeks an experienced DFT Architect to lead design-for-test strategy across complex ASIC/SOC designs, defining SOC-level DFT architecture and implementing scan, MBIST, compression, and boundary scan.

You will collaborate with RTL, Physical Design, Verification, and Product Engineering to drive DFT planning, signoff, and optimizations, while mentoring junior engineers and advancing automation across projects.