Senior ASIC DFT Engineer - SoC Test and Yield Lead

Socket.dev; San Jose (CA); On-site; USD 180,000 - 260,000; Full time

Benefits offered by this job

Equity grants

Annual equity awards

Competitive benefits package

Job summary

Broadcom's Development Center in San Jose seeks a senior DFT engineer to lead DFT programs from specification to production release. You will handle DFT architecture, test insertion, pattern generation, and post-silicon debugging across multiple designs, interfacing with a global team.

The role requires strong DFT background (ATPG/Scan/BIST), Verilog, and memory BIST experience, with collaboration across test, design, and reliability groups.

Qualifications

• Bachelor's degree or higher with 12+ years related experience.
• Strong DFT background including IO/Analog DFT, ATPG, Scan, BIST.
• Experience with Scan Insertion and scan compression tools (DFT Compiler, Mentor TestKompress).
• Verilog coding, testbench generation and simulation.
• Memory BIST insertion and verification on embedded memories (SRAM, CAM, eDRAM, ROM).
• IEEE1149.1/1149.6 boundary scan knowledge and practice.
• Excellent debugging, problem-solving, and communication skills.

Responsibilities

• Understand Broadcom/customer DFT feature requirements and define DFT specifications for the ASIC.
• Implement DFT including Scan, MBIST, TAP, LBIST, IO, SerDes integration.
• Pattern generation and verification at chip level; rapid bring-up at ATE and RMA support.
• Collaborate with STA/DI Engineers for test closure.
• Generate, verify, and debug Test vectors before tape release.
• Validate/debug Test vectors on ATE during silicon bring-up.
• Assist with silicon failure analysis, diagnostics, and yield improvements.
• Interface with customer, physical design, and test/Manufacturing teams globally.
• Work with IP DFT engineers and other stakeholders.
• Debug customer-returned parts on ATE.
• Innovate new DFT solutions for 3nm and beyond.
• Automate DFT and Test Vector Generation flows.

Skills

DFT

IO DFT

ATPG

Scan Insertion

BIST

Verilog

Memory BIST

IEEE1149.1

IEEE1149.6

TetraMax

Fastscan

Serdes

DDR

PCIe

CXL IOBIST

Problem Solving

Communication

Project Management

Education

Bachelor's degree

Master's degree

Tools

TetraMax

Fastscan

Job description

Broadcom's Development Center in San Jose seeks a senior DFT engineer to lead DFT programs from specification to production release. You will handle DFT architecture, test insertion, pattern generation, and post-silicon debugging across multiple designs, interfacing with a global team.

The role requires strong DFT background (ATPG/Scan/BIST), Verilog, and memory BIST experience, with collaboration across test, design, and reliability groups.