Senior DFT Architect for Mixed-Signal SoCs

K2 Space Corporation; United States; On-site; USD 170,000 - 250,000; Full time

Benefits offered by this job

Equity

Medical/dental/vision coverage

Life insurance

Paid parental leave

Paid time off

Job summary

K2 Space Corporation is seeking a highly experienced Senior Design-for-Test (DFT) Engineer to lead DFT architecture and implementation for complex mixed-signal SoCs. You will drive RTL-level DFT insertion, MBIST/LBIST, and ATPG strategy across digital and mixed-signal domains.

Collaborating with design, verification, and physical design teams, you will ensure high test coverage, manufacturability, and first-pass silicon success while contributing to automation and flow improvements.

Qualifications

• 7+ years of experience in DFT for complex SoCs.
• Strong hands-on experience with RTL DFT insertion and ATPG tools.
• Experience with MBIST/LBIST and memory test methods.
• Knowledge of IEEE 1149.x (JTAG) standards.
• Ability to collaborate with RTL, DV, and PD teams.
• Excellent debugging across RTL, gate-level, and silicon.

Responsibilities

• Define and implement DFT architecture for mixed-signal SoCs, including MBIST, LBIST, scan.
• Lead RTL-level DFT insertion and optimization, test point insertion, and low-power DFT techniques.
• Own ATPG flow development and pattern generation with coverage closure.
• Develop DFT strategies for mixed-signal blocks, including analog interfaces and BIST.
• Collaborate with RTL, DV, PD teams to ensure clean RTL and gate-level DFT integration.
• Drive DFT verification and signoff, including coverage metrics and rule compliance.
• Support silicon bring-up and yield ramp through failure analysis and pattern correlation.
• Contribute to automation and flow improvements.

Skills

DFT Architecture

RTL DFT Insertion

ATPG Flow Development

MBIST/LBIST Experience

Mixed-signal DFT

RTL/Gate-Si Debugging

Automation Scripting

Education

B.S. in Electrical Engineering or related field

M.S. in Electrical Engineering (preferred)

Tools

ATPG Tools

MBIST/LBIST Tooling

JTAG/Boundary Scan Tooling

Job description

K2 Space Corporation is seeking a highly experienced Senior Design-for-Test (DFT) Engineer to lead DFT architecture and implementation for complex mixed-signal SoCs. You will drive RTL-level DFT insertion, MBIST/LBIST, and ATPG strategy across digital and mixed-signal domains.

Collaborating with design, verification, and physical design teams, you will ensure high test coverage, manufacturability, and first-pass silicon success while contributing to automation and flow improvements.