Senior DFT Architect: 2.5D/3D ICs & ATE Bring-up

NVIDIA Corporation; Santa Clara, Northern (CA, KY); Hybrid; USD 168,000 - 311,000; Full time

Benefits offered by this job

Equity

Hybrid work model

Comprehensive benefits

Job summary

NVIDIA invites an experienced Senior DFT Engineer to shape the future of silicon test across advanced GPUs and SoCs. You will design and prototype test architectures, collaborating with CAD teams and EDA vendors to push the boundaries from RTL to post-silicon ATE bring-up.

The role emphasizes ownership of the ATPG lifecycle, mentoring junior engineers, and delivering world-class quality across multi-chiplet platforms.

Qualifications

• MS/PhD or equivalent in Electrical Engineering or related field.
• 6+ years of hands-on experience in Design-For-Test (DFT).
• Deep knowledge of DFT tools, methodologies, and test strategies for complex, large-scale designs.
• Strong experience with industry standard ATPG tools.
• Clear, effective communicator—strong written and verbal skills.
• Passion for mentoring and scaling technical excellence in a team.

Responsibilities

• Develop and deploy Industry-leading test methodologies on NVIDIA’s next-generation silicon platforms.
• Collaborate with leading EDA vendors to shape tool capabilities that meet NVIDIA’s ambitious design goals, and partner with internal CAD teams to drive scalable, automated solutions.
• Co-architect novel DFT strategies alongside VLSI and Product Engineering teams to push the boundaries of silicon test innovation.
• Own the full ATPG lifecycle—verification, coverage analysis, pattern generation, and ATE bring-up—across NVIDIA’s full product portfolio.
• Guide and mentor junior engineers, helping them navigate complex design trade-offs to achieve world-class quality and efficiency.

Skills

DFT experience

ATPG tools

DFT methodologies

Communication

Mentoring

Education

MS/PhD in Electrical Engineering

Tools

DFT Tools

ATPG Tools

EDA tool flows

Automation scripting

Job description

NVIDIA invites an experienced Senior DFT Engineer to shape the future of silicon test across advanced GPUs and SoCs. You will design and prototype test architectures, collaborating with CAD teams and EDA vendors to push the boundaries from RTL to post-silicon ATE bring-up.

The role emphasizes ownership of the ATPG lifecycle, mentoring junior engineers, and delivering world-class quality across multi-chiplet platforms.