Senior DFT Architect for Next-Gen Multi-Chiplet Silicon

Socket.dev; Santa Clara (TX); Hybrid; USD 168,000 - 311,000; Full time

Benefits offered by this job

Equity

Benefits

Job summary

NVIDIA is seeking an exceptional DFT Engineer to shape the future of compute, spanning 2.5D/3D ICs, RTL to ATE bring-up, and mentoring junior engineers.

Role focuses on developing industry-leading test methodologies, collaborating with EDA vendors, and co-architecting DFT strategies with VLSI and Product teams. Candidates need MS/PhD in EE and 6+ years in DFT, with strong ATPG experience. This is a hybrid role with equity and benefits.

Qualifications

• MS/PhD or equivalent experience in Electrical Engineering or a related field.
• 6+ years of hands-on experience in Design-For-Test (DFT).
• Deep knowledge of DFT tools, methodologies, and test strategies for complex, large-scale designs.
• Strong experience with industry standard ATPG tools.
• Clear, effective communicator—strong written and verbal skills.
• Passion for mentoring and scaling technical excellence in a team.

Responsibilities

• Develop and deploy Industry-leading test methodologies on NVIDIA’s next-generation silicon platforms.
• Collaborate with leading EDA vendors to shape tool capabilities and partner with CAD teams to drive scalable automation.
• Co-architect novel DFT strategies with VLSI and Product Engineering teams to push silicon test innovation.
• Own the full ATPG lifecycle—verification, coverage analysis, pattern generation, and ATE bring-up—across NVIDIA’s product portfolio.
• Guide and mentor junior engineers to navigate design trade-offs for world-class quality and efficiency.

Skills

DFT

ATPG tools

EDA tool flows

Mentoring

Communication

Education

MS/PhD in Electrical Engineering

Tools

DFT tool suites

EDA tool suites

Scripting (Python)

Job description

NVIDIA is seeking an exceptional DFT Engineer to shape the future of compute, spanning 2.5D/3D ICs, RTL to ATE bring-up, and mentoring junior engineers.

Role focuses on developing industry-leading test methodologies, collaborating with EDA vendors, and co-architecting DFT strategies with VLSI and Product teams. Candidates need MS/PhD in EE and 6+ years in DFT, with strong ATPG experience. This is a hybrid role with equity and benefits.