Lead DFT Architect for Next-Gen Silicon & Automated Testing

Jobtailor; California (MO); On-site; USD 170,000 - 230,000; Full time

Job summary

NVIDIA in the United States is seeking a senior DFT/ATPG engineer to develop and deploy industry-leading test methodologies for next-generation silicon platforms, collaborating with top EDA vendors and internal CAD teams to drive scalable, automated solutions.

You will co-architect novel DFT strategies with VLSI and Product Engineering, own the full ATPG lifecycle from verification to ATE bring-up, and mentor junior engineers while scaling technical excellence across the team.

Qualifications

• MS/PhD in Electrical Engineering or related field.
• 6+ years hands-on experience in Design-For-Test (DFT).
• Strong communication and mentoring skills.

Responsibilities

• Own the ATPG lifecycle: verification, coverage analysis, pattern generation, and ATE bring-up.
• Co-architect novel DFT strategies alongside VLSI and Product Engineering teams.
• Collaborate with leading EDA vendors and internal CAD teams to drive scalable, automated solutions.
• Mentor junior engineers and guide org-wide changes.

Skills

DFT Methodologies

ATPG Tools

Silicon Testing

EDA Tool Flows

Multi-Chiplet Architectures

2.5D/3D ICs

Pattern Generation

Coverage Analysis

Verification

Programming Languages

AI for Automation

Mentoring

Team Collaboration

Effective Communication

Education

MS/PhD in Electrical Engineering

Tools

ATPG Tools

EDA Tool Flows

Job description

NVIDIA in the United States is seeking a senior DFT/ATPG engineer to develop and deploy industry-leading test methodologies for next-generation silicon platforms, collaborating with top EDA vendors and internal CAD teams to drive scalable, automated solutions.

You will co-architect novel DFT strategies with VLSI and Product Engineering, own the full ATPG lifecycle from verification to ATE bring-up, and mentor junior engineers while scaling technical excellence across the team.