Senior DFT/DFX Engineer - Test Architect for AI Chips

Nvidia Corporation in; Santa Clara (CA); Hybrid; USD 168,000 - 311,000; Full time

Benefits offered by this job

Equity compensation

Comprehensive benefits

Hybrid work model

Job summary

NVIDIA in Santa Clara, CA is seeking a Senior DFT Engineer to drive design-for-test methodologies for high‑end semiconductor products. You will own DFX architecture across test access, memory BIST, and scan compression while collaborating with system, RTL, CAD, and verify teams.

This role requires 8+ years in DFT or related domains, strong scripting, and experience with ATE, ISO26262 safety diagnostic concepts, and silicon bring-up.

Qualifications

• 8+ years in DFT or related domains.
• Strong knowledge of scan test plans, BIST, fault modeling, ATPG and fault simulation.
• Excellent analytical skills for verification and validation of test patterns on complex designs.
• Experience with cross functional RTL, clocks, STA, place-n-route and power trade-offs.

Responsibilities

• Own and work with cross functional teams implementing state-of-the-art DFT architectures (test access, IO BIST, memory BIST, scan compression).
• Develop and deploy DFX architectures across products including high speed test access and in-system test.
• Craft DFX architecture to meet system safety diagnostic test quality and in-field test quality goals.
• Collaborate with system, chip, CAD, VLSI, SW, and operations teams to productize methodologies.
• Deliver efficient workflows and tools to enable features on leading processors for DL, gaming, HPC and more.
• Mentor junior engineers on test designs and trade-offs.

Skills

Perl

Python

Tcl

DFT methods

Cross-functional teamwork

Scripting

Education

BSEE

MSEE

PhD in DFT/related field

Job description

NVIDIA in Santa Clara, CA is seeking a Senior DFT Engineer to drive design-for-test methodologies for high‑end semiconductor products. You will own DFX architecture across test access, memory BIST, and scan compression while collaborating with system, RTL, CAD, and verify teams.

This role requires 8+ years in DFT or related domains, strong scripting, and experience with ATE, ISO26262 safety diagnostic concepts, and silicon bring-up.