Senior DFT Engineer

Jobtailor; California (MO); On-site; USD 170,000 - 230,000; Full time

Job summary

NVIDIA in the United States is seeking a senior DFT/ATPG engineer to develop and deploy industry-leading test methodologies for next-generation silicon platforms, collaborating with top EDA vendors and internal CAD teams to drive scalable, automated solutions.

You will co-architect novel DFT strategies with VLSI and Product Engineering, own the full ATPG lifecycle from verification to ATE bring-up, and mentor junior engineers while scaling technical excellence across the team.

Qualifications

• MS/PhD in Electrical Engineering or related field.
• 6+ years hands-on experience in Design-For-Test (DFT).
• Strong communication and mentoring skills.

Responsibilities

• Own the ATPG lifecycle: verification, coverage analysis, pattern generation, and ATE bring-up.
• Co-architect novel DFT strategies alongside VLSI and Product Engineering teams.
• Collaborate with leading EDA vendors and internal CAD teams to drive scalable, automated solutions.
• Mentor junior engineers and guide org-wide changes.

Skills

DFT Methodologies

ATPG Tools

Silicon Testing

EDA Tool Flows

Multi-Chiplet Architectures

2.5D/3D ICs

Pattern Generation

Coverage Analysis

Verification

Programming Languages

AI for Automation

Mentoring

Team Collaboration

Effective Communication

Education

MS/PhD in Electrical Engineering

Tools

ATPG Tools

EDA Tool Flows

Job description

• Develop and deploy industry-leading test methodologies on NVIDIA’s next-generation silicon platforms
• Collaborate with leading EDA vendors to shape tool capabilities and partner with internal CAD teams to drive scalable, automated solutions
• Co-architect novel DFT strategies alongside VLSI and Product Engineering teams
• Own the full ATPG lifecycle: verification, coverage analysis, pattern generation, and ATE bring-up
• Guide and mentor junior engineers
• Design and prototype test architectures for reticle-sized, multi-chiplet products from RTL through verification to post-silicon ATE bring-up

Requirements

• MS/PhD or equivalent experience in Electrical Engineering or a related field
• 6+ years of hands-on experience in Design-For-Test (DFT)
• Deep knowledge of DFT tools, methodologies, and test strategies for complex, large-scale designs
• Strong experience with industry standard ATPG tools
• Clear, effective communicator—strong written and verbal skills
• Passion for mentoring and scaling technical excellence in a team
• Experience with 2.5D/3D ICs, multi-chiplet architectures, or reticle-sized designs
• Background in developing or enhancing EDA tool flows
• Experience with Silicon testing and Automatic Test Equipment (ATE)
• Expertise in using programming languages and AI for automation
• Personal success stories in leading org wide changes

Core Competencies

Demonstrates expertise in Design-For-Test (DFT) methodologies and tools, with a strong focus on the ATPG lifecycle and silicon testing. Proven ability to mentor junior engineers and collaborate effectively with cross-functional teams to drive innovative test architectures.

Highest-signal resume keywords

• Design-For-Test (DFT)
• ATPG Tools
• Silicon Testing
• EDA Tool Flows
• Mentoring

Hard Skills

• DFT Methodologies
• Pattern Generation
• Coverage Analysis
• Verification
• ATE Bring-Up
• Programming Languages
• AI for Automation
• Multi-Chiplet Architectures
• 2.5D/3D ICs
• Test Architectures

Soft Skills

• Effective Communication
• Mentoring
• Team Collaboration

Certifications & Qualifications

• MS/PhD in Electrical Engineering

Industry Keywords

• Silicon Platforms
• EDA Vendors
• VLSI
• Reticle-Sized Designs
• Automated Solutions