Senior Design Verification Engineer - Hybrid (SystemVerilog/UVM)

ams-OSRAM AG; Plano (TX); Hybrid; USD 140,000 - 190,000; Full time

Job summary

ams OSRAM USA Inc. is seeking a Senior Staff Design Verification Engineer to drive verification for complex digital and mixed‑signal ICs. You will lead DV planning, develop UVM environments, and build scoreboards, coverage models, and debug strategies.

The role requires expert SystemVerilog/UVM, strong coverage-driven verification experience, and collaboration with Design, Architecture, AMS, Firmware, and Validation teams. Hybrid work model with 8+ years of relevant experience preferred.

Qualifications

• Master's degree with 8+ years experience preferred.
• Bachelor's degree with 10+ years experience minimum.
• Expert-level SystemVerilog and UVM proficiency.
• Strong knowledge of functional coverage development and coverage-driven verification.
• Experience debugging RTL, testbench, and integration issues.
• Familiarity with scripting languages: Python, Perl, Tcl.

Responsibilities

• Develop DV plans, verification strategies, and signoff criteria.
• Architect, implement, and maintain reusable UVM-based environments.
• Create scoreboards, monitors, and coverage models.
• Perform full-chip verification and analyze architecture specs.
• Collaborate with Design, Architecture, AMS, Firmware, and Validation teams.

Skills

SystemVerilog

UVM

Functional coverage

Debugging

Scoreboards

Monitors

Agents

Coverage models

Verification planning

RTL verification

ASIC/SoC architectures

Python

Perl

Tcl

Education

Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related technical field

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related technical field

Job description

ams OSRAM USA Inc. is seeking a Senior Staff Design Verification Engineer to drive verification for complex digital and mixed‑signal ICs. You will lead DV planning, develop UVM environments, and build scoreboards, coverage models, and debug strategies.

The role requires expert SystemVerilog/UVM, strong coverage-driven verification experience, and collaboration with Design, Architecture, AMS, Firmware, and Validation teams. Hybrid work model with 8+ years of relevant experience preferred.