Senior DV Architect: Digital IC Verification Lead

ams-OSRAM USA Inc.; Plano (TX); On-site; USD 140,000 - 190,000; Full time

Job summary

ams OSRAM USA Inc. in Plano, TX seeks a Senior Staff Design Verification Engineer to lead verification for complex semiconductor products.

The role centers on SystemVerilog/UVM-based verification, driving planning, coverage, and debugging from spec to tapeout in a senior IC environment. You will architect reusable verification environments, develop assertions and scoreboards, perform full-chip verification, and collaborate with Design, Architecture, AMS, Firmware, and Validation teams to deliver

Qualifications

• Master's or Bachelor's degree in a related technical field with 8+ or 10+ years of experience.
• Expert-level SystemVerilog and UVM; strong coverage and debug skills.
• Experience in ASIC/SoC verification from spec to tapeout.

Responsibilities

• Develop comprehensive DV plans, verification strategies, and signoff criteria.
• Architect, implement, and maintain reusable UVM environments.
• Develop assertions, scoreboards, checkers, and coverage models.
• Perform block-, subsystem-, and full-chip verification.
• Analyze architecture specs and derive verification requirements.
• Debug complex RTL, testbench, and integration issues.
• Collaborate with Design, Architecture, AMS, Firmware and Validation teams.
• Communicate verification status, risks, and closure metrics.

Skills

SystemVerilog

UVM

Functional coverage

Debug root-cause

Scoreboards

Monitors

Agents

Coverage models

Block-level verification

Full-chip verification

Verification planning

ASIC/SoC

RTL review

Python scripting

Education

Master's degree in Electrical/Computer Engineering or related field

Bachelor's degree in Electrical/Computer Engineering or related field

Job description

ams OSRAM USA Inc. in Plano, TX seeks a Senior Staff Design Verification Engineer to lead verification for complex semiconductor products.

The role centers on SystemVerilog/UVM-based verification, driving planning, coverage, and debugging from spec to tapeout in a senior IC environment. You will architect reusable verification environments, develop assertions and scoreboards, perform full-chip verification, and collaborate with Design, Architecture, AMS, Firmware, and Validation teams to deliver