Senior SystemVerilog DV Engineer — UVM Expert

OSI USA Danvers; Plano (TX); On-site; USD 150,000 - 190,000; Full time

Job summary

ams OSRAM is seeking a Senior Staff Design Verification Engineer to drive verification across complex digital and mixed-signal ICs. The role emphasizes SystemVerilog/UVM expertise, verification planning, and end-to-end execution from specification to tapeout.

You will architect reusable UVM environments, develop coverage models and scoreboards, and collaborate with design, firmware, and validation teams. A senior individual contributor role with leadership potential.

Qualifications

• Master's degree or higher in a relevant engineering/computer science field with 8+ years of industry experience.
• Bachelor's degree in a technical field with 10+ years of industry experience is the minimum qualification.
• Expert knowledge of SystemVerilog/UVM, functional coverage, and DV planning.

Responsibilities

• Develop DV plans, strategies, and coverage goals with signoff criteria.
• Identify and mitigate functional verification risks and issues.
• Architect, implement, and maintain reusable UVM environments.
• Develop assertions, scoreboards, checkers, and coverage models.
• Perform block-, subsystem-, and full-chip verification.
• Analyze architecture specifications to derive verification requirements.
• Debug RTL, testbench, and integration issues.
• Collaborate with Design, Architecture, AMS, Firmware, and Validation teams.
• Participate in design and verification reviews and communicate status.

Skills

SystemVerilog & UVM

Functional coverage

Debug & root-cause analysis

Scoreboards/Monitors/Agents

Block/subsystem/full-chip verification

Verification planning & signoff

Digital design fundamentals & ASIC/SoC

RTL review & verification risks

Python/Perl/Tcl scripting

Education

Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field

Job description

ams OSRAM is seeking a Senior Staff Design Verification Engineer to drive verification across complex digital and mixed-signal ICs. The role emphasizes SystemVerilog/UVM expertise, verification planning, and end-to-end execution from specification to tapeout.

You will architect reusable UVM environments, develop coverage models and scoreboards, and collaborate with design, firmware, and validation teams. A senior individual contributor role with leadership potential.