Senior Design Verification Engineer

OSI USA Danvers; Plano (TX); On-site; USD 150,000 - 190,000; Full time

Job summary

ams OSRAM is seeking a Senior Staff Design Verification Engineer to drive verification across complex digital and mixed-signal ICs. The role emphasizes SystemVerilog/UVM expertise, verification planning, and end-to-end execution from specification to tapeout.

You will architect reusable UVM environments, develop coverage models and scoreboards, and collaborate with design, firmware, and validation teams. A senior individual contributor role with leadership potential.

Qualifications

• Master's degree or higher in a relevant engineering/computer science field with 8+ years of industry experience.
• Bachelor's degree in a technical field with 10+ years of industry experience is the minimum qualification.
• Expert knowledge of SystemVerilog/UVM, functional coverage, and DV planning.

Responsibilities

• Develop DV plans, strategies, and coverage goals with signoff criteria.
• Identify and mitigate functional verification risks and issues.
• Architect, implement, and maintain reusable UVM environments.
• Develop assertions, scoreboards, checkers, and coverage models.
• Perform block-, subsystem-, and full-chip verification.
• Analyze architecture specifications to derive verification requirements.
• Debug RTL, testbench, and integration issues.
• Collaborate with Design, Architecture, AMS, Firmware, and Validation teams.
• Participate in design and verification reviews and communicate status.

Skills

SystemVerilog & UVM

Functional coverage

Debug & root-cause analysis

Scoreboards/Monitors/Agents

Block/subsystem/full-chip verification

Verification planning & signoff

Digital design fundamentals & ASIC/SoC

RTL review & verification risks

Python/Perl/Tcl scripting

Education

Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field

Job description

Your tasks

We are seeking a highly motivated and experienced Senior Staff Design Verification Engineer to drive and collaborate on verification activities for complex semiconductor products. This is a senior individual contributor role focused on delivering high-quality verification solutions for advanced digital and mixed-signal integrated circuits.

The ideal candidate will be an expert in SystemVerilog and UVM-based verification methodologies, capable of independently driving verification planning, execution, coverage closure, and debug activities from specification through tapeout. The role offers the opportunity to grow into technical leadership through influence, expertise, and ownership of critical verification deliverables.

Key Responsibilities:Verification Planning and Execution

• Develop comprehensive Design Verification (DV) plans and verification strategies; define verification scope, coverage goals and signoff criteria
• Identify and mitigate functional verification risks

Verification Environment Development

• Architect, implement, and maintain reusable UVM-based environments
• Develop assertions, scoreboards, checkers, and coverage models

Design Verification

• Perform block-level, subsystem-level, and full-chip verification
• Analyze architecture specifications and derive verification requirements
• Debug complex RTL, testbench, and integration issues

Cross-Functional Collaboration

• Work closely with Design, Architecture, AMS, Firmware, and Validation teams
• Participate in design reviews and verification reviews; support customer technical discussions
• Communicate verification status, risks, and closure metrics

Who we are looking for

Education and Experience

• Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field with 8+ years of relevant industry experience (preferred)
• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field with 10+ years of relevant industry experience (minimum qualification)

Required Technical Skills

• Expert-level proficiency in SystemVerilog and UVM
• Strong knowledge of functional coverage development and coverage-driven verification
• Strong debug and root-cause analysis skills
• Creation of scoreboards, monitors, agents, predictors, and coverage models
• Block-level, subsystem-level, and full-chip verification experience
• Verification planning and execution from specification through signoff
• Strong understanding of digital design fundamentals and ASIC/SoC architectures
• Experience reviewing RTL and identifying verification risks
• Familiarity with scripting languages such as Python, Perl, or Tcl

Why Join Us

You will contribute to the verification of next-generation sensor and semiconductor products while working with a highly experienced engineering team. This role offers significant technical ownership, opportunities to shape verification methodology, and a path toward future technical leadership within the organization.

ams OSRAM is an Equal Employment Opportunity Employer. All qualified applicants will receive
consideration for employment without regard to race, color, religion, sex, sexual orientation,
national origin, age, disability, gender identity, or veteran status. If you are an individual with a
disability and require a reasonable accommodation to complete any part of the application process,
please contact the local Recruiter, Hiring Manager or HR Manager in the location in which you are
applying for.