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LanceSoft, Inc. in Santa Clara, CA is seeking a Senior Design Verification Engineer with 8+ years of SystemVerilog and UVM experience to lead IP verification efforts.
The role emphasizes IO/PHY verification, formal methods, and mentoring DV teams across geographies, collaborating with design and post-Si teams to ensure bug-free silicon.
Pay rate range: $85/hr to $107/hr on W2.
Looking for 8+ years SystemVerilog UVM experience, IP design verification and formal verification.
We are seeking a seasoned verification lead with expertise or significant interest in IO/PHY verification. You have had significant success driving IP verification, UVM and SystemVerilog. This senior role will stretch you as you lead DV teams in new directions, network with our world‑class design/DV teams.
You have excellent communication and presentation skills, demonstrated through technical publications, presentations, trainings, executive briefings, etc. You are highly adept at collaboration among top‑thinkers and engineers alike, ready to mentor and guide, and help to elevate the knowledge and skills of the team around you.
LanceSoft is a certified Minority Business Enterprise (MBE) and an equal opportunity employer. We prohibit discrimination and harassment of any kind based on race, color, sex, religion, sexual orientation, national origin, disability, genetic information, pregnancy, or any other protected characteristic as outlined by federal, state, or local laws.
This policy applies to all employment practices within our organization, including hiring, recruiting, promotion, termination, layoff, recall, leave of absence, compensation, benefits, training, and apprenticeship. LanceSoft makes hiring decisions based solely on qualifications, merit, and business needs at the time.