Turn this role into an interview — a resume and cover letter built around what this employer wants.
L&T Technology Services in San Jose seeks DV verification engineers to verify complex internal IP blocks within SoC environments, focusing on compute engines, accelerators, and custom logic. You will develop UVM-based verification environments, create test plans and coverage models, verify RTL designs, debug testbenches, and drive coverage closure across functional and code domains.
Strong hands-on with SystemVerilog and UVM, plus experience in block-level verification and debugging tools, are
We are seeking DV engineers to verify complex internal IP blocks such as compute engines, accelerators, and custom logic within SoC environments.
The expected salary range for this position is between $140K - $200K annually. The actual salary may vary based upon several factors including, but not limited to, relevant skills/experience, time in role, base salary of internal peers, prior performance, business line, and geographic/office location.