Design Verification Engineer - CPU Subsystem

Yoh, A Day & Zimmermann Company; Santa Clara (CA); On-site; USD 96,432 - 137,760; Full time

Job summary

An established industry player is seeking a Design Verification Engineer to ensure the quality and reliability of cutting-edge IP solutions. In this pivotal role, you will leverage your expertise in System Verilog and UVM to develop verification environments and execute comprehensive test plans. Your contributions will directly impact the functional verification at the RTL level, driving improvements through coverage analysis and the development of Universal Verification Components. This position offers an exciting opportunity to work independently on complex protocols and contribute to innovative projects in a dynamic engineering environment.

Qualifications

• 7+ years of experience in DV & verification methodologies.
• Strong proficiency in System Verilog & UVM required.

Responsibilities

• Define verification plans & develop DV environments in System Verilog.
• Create & execute test plans to ensure quality of IP solutions.

Skills

System Verilog

UVM

C++

Problem-solving

Communication

Job description

Location: Santa Clara, United States
Sector: Engineering
Salary: $70.00 to $100.00 per hour

Design Verification Engineer - CPU Subsystem
Looking for a Design Verification Engineer to play a key role in ensuring the quality & reliability of the company's IP solutions. Requires strong expertise in System Verilog (SV) & UVM, with a focus on developing verification environments, executing test plans, & driving functional verification at the RTL level. The ideal person would have experience with coverage analysis, UVC development, & verification of complex protocols like AXI & CHI, with additional knowledge of cache & NOC interconnect verification being a plus.

Scope:

1. Define verification plans & develop DV environments independently in System Verilog (SV)/UVM.
2. Knowledge of C++ is preferred.
3. Create & execute test plans to ensure the quality/reliability of the company's IP solutions.
4. Expertise in System Verilog & UVM methodologies.
5. Perform functional verification at the RTL level, including coverage analysis & improvement.
6. Develop Universal Verification Components (UVCs) from scratch.
7. Experience with Cache, NOC Interconnect verification is desirable.
8. Knowledge of bus protocols – AXI, CHI etc. are added advantages.

Required:

1. 7+ years of experience in DV & verification methodologies.
2. Strong proficiency in System Verilog & UVM.
3. Ability to work independently & drive projects to completion.
4. Experience in IP development, particularly in DFD IP, is desirable.
5. Excellent problem-solving & communication skills.

Estimated Min Rate: $70.00
Estimated Max Rate: $100.00

Note: Any pay ranges displayed are estimations. Actual pay is determined by an applicant's experience, technical expertise, and other qualifications as listed in the job description. All qualified applicants are welcome to apply.

Yoh, a Day & Zimmermann company, is an Equal Opportunity Employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran.

Visit https://www.yoh.com/applicants-with-disabilities to contact us if you are an individual with a disability and require accommodation in the application process.

For California applicants, qualified applicants with arrest or conviction records will be considered for employment in accordance with the Los Angeles County Fair Chance Ordinance for Employers and the California Fair Chance Act. All of the material job duties described in this posting are job duties for which a criminal history may have a direct, adverse, and negative relationship potentially resulting in the withdrawal of a conditional offer of employment.